PSG1218.dts 1.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119
  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. #include <dt-bindings/input/input.h>
  4. / {
  5. compatible = "PSG1218", "ralink,mt7620a-soc";
  6. model = "Phicomm PSG1218";
  7. gpio-leds {
  8. compatible = "gpio-leds";
  9. blue {
  10. label = "psg1218:blue:status";
  11. gpios = <&gpio0 10 1>;
  12. };
  13. yellow {
  14. label = "psg1218:yellow:status";
  15. gpios = <&gpio0 11 1>;
  16. };
  17. red {
  18. label = "psg1218:red:status";
  19. gpios = <&gpio0 8 0>;
  20. };
  21. };
  22. gpio-keys-polled {
  23. compatible = "gpio-keys-polled";
  24. #address-cells = <1>;
  25. #size-cells = <0>;
  26. poll-interval = <20>;
  27. reset {
  28. label = "reset";
  29. gpios = <&gpio0 1 1>;
  30. linux,code = <KEY_RESTART>;
  31. };
  32. };
  33. };
  34. &gpio0 {
  35. status = "okay";
  36. };
  37. &spi0 {
  38. status = "okay";
  39. m25p80@0 {
  40. #address-cells = <1>;
  41. #size-cells = <1>;
  42. compatible = "jedec,spi-nor";
  43. reg = <0>;
  44. spi-max-frequency = <10000000>;
  45. partition@0 {
  46. label = "u-boot";
  47. reg = <0x0 0x30000>;
  48. read-only;
  49. };
  50. partition@20000 {
  51. label = "u-boot-env";
  52. reg = <0x30000 0x10000>;
  53. read-only;
  54. };
  55. factory: partition@30000 {
  56. label = "factory";
  57. reg = <0x40000 0x10000>;
  58. read-only;
  59. };
  60. partition@40000 {
  61. label = "firmware";
  62. reg = <0x50000 0x7b0000>;
  63. };
  64. };
  65. };
  66. &pinctrl {
  67. state_default: pinctrl0 {
  68. gpio {
  69. ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled", "nd_sd";
  70. ralink,function = "gpio";
  71. };
  72. pa {
  73. ralink,group = "pa";
  74. ralink,function = "pa";
  75. };
  76. };
  77. };
  78. &ethernet {
  79. pinctrl-names = "default";
  80. pinctrl-0 = <&ephy_pins>;
  81. mtd-mac-address = <&factory 0x28>;
  82. mediatek,portmap = "llllw";
  83. };
  84. &pcie {
  85. status = "okay";
  86. pcie-bridge {
  87. mt76@0,0 {
  88. reg = <0x0000 0 0 0 0>;
  89. device_type = "pci";
  90. mediatek,mtd-eeprom = <&factory 0x8000>;
  91. ieee80211-freq-limit = <5000000 6000000>;
  92. };
  93. };
  94. };
  95. &wmac {
  96. ralink,mtd-eeprom = <&factory 0>;
  97. };