040-ARM-dts-imx-ventana-add-pwm-nodes.patch 4.8 KB

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  1. --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
  2. +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
  3. @@ -174,6 +174,24 @@
  4. status = "okay";
  5. };
  6. +&pwm2 {
  7. + pinctrl-names = "default";
  8. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  9. + status = "disabled";
  10. +};
  11. +
  12. +&pwm3 {
  13. + pinctrl-names = "default";
  14. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  15. + status = "disabled";
  16. +};
  17. +
  18. +&pwm4 {
  19. + pinctrl-names = "default";
  20. + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
  21. + status = "disabled";
  22. +};
  23. +
  24. &uart1 {
  25. pinctrl-names = "default";
  26. pinctrl-0 = <&pinctrl_uart1>;
  27. @@ -294,6 +312,24 @@
  28. >;
  29. };
  30. + pinctrl_pwm2: pwm2grp {
  31. + fsl,pins = <
  32. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  33. + >;
  34. + };
  35. +
  36. + pinctrl_pwm3: pwm3grp {
  37. + fsl,pins = <
  38. + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  39. + >;
  40. + };
  41. +
  42. + pinctrl_pwm4: pwm4grp {
  43. + fsl,pins = <
  44. + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
  45. + >;
  46. + };
  47. +
  48. pinctrl_uart1: uart1grp {
  49. fsl,pins = <
  50. MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
  51. --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
  52. +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
  53. @@ -282,6 +282,18 @@
  54. status = "okay";
  55. };
  56. +&pwm2 {
  57. + pinctrl-names = "default";
  58. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  59. + status = "disabled";
  60. +};
  61. +
  62. +&pwm3 {
  63. + pinctrl-names = "default";
  64. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  65. + status = "disabled";
  66. +};
  67. +
  68. &pwm4 {
  69. pinctrl-names = "default";
  70. pinctrl-0 = <&pinctrl_pwm4>;
  71. @@ -436,6 +448,18 @@
  72. >;
  73. };
  74. + pinctrl_pwm2: pwm2grp {
  75. + fsl,pins = <
  76. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  77. + >;
  78. + };
  79. +
  80. + pinctrl_pwm3: pwm3grp {
  81. + fsl,pins = <
  82. + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  83. + >;
  84. + };
  85. +
  86. pinctrl_pwm4: pwm4grp {
  87. fsl,pins = <
  88. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  89. --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
  90. +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
  91. @@ -287,6 +287,18 @@
  92. };
  93. };
  94. +&pwm2 {
  95. + pinctrl-names = "default";
  96. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  97. + status = "disabled";
  98. +};
  99. +
  100. +&pwm3 {
  101. + pinctrl-names = "default";
  102. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  103. + status = "disabled";
  104. +};
  105. +
  106. &pwm4 {
  107. pinctrl-names = "default";
  108. pinctrl-0 = <&pinctrl_pwm4>;
  109. @@ -442,6 +454,18 @@
  110. >;
  111. };
  112. + pinctrl_pwm2: pwm2grp {
  113. + fsl,pins = <
  114. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  115. + >;
  116. + };
  117. +
  118. + pinctrl_pwm3: pwm3grp {
  119. + fsl,pins = <
  120. + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  121. + >;
  122. + };
  123. +
  124. pinctrl_pwm4: pwm4grp {
  125. fsl,pins = <
  126. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  127. --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
  128. +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
  129. @@ -378,6 +378,24 @@
  130. };
  131. };
  132. +&pwm1 {
  133. + pinctrl-names = "default";
  134. + pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
  135. + status = "disabled";
  136. +};
  137. +
  138. +&pwm2 {
  139. + pinctrl-names = "default";
  140. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  141. + status = "disabled";
  142. +};
  143. +
  144. +&pwm3 {
  145. + pinctrl-names = "default";
  146. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  147. + status = "disabled";
  148. +};
  149. +
  150. &pwm4 {
  151. pinctrl-names = "default";
  152. pinctrl-0 = <&pinctrl_pwm4>;
  153. @@ -537,6 +555,24 @@
  154. >;
  155. };
  156. + pinctrl_pwm1: pwm1grp {
  157. + fsl,pins = <
  158. + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
  159. + >;
  160. + };
  161. +
  162. + pinctrl_pwm2: pwm2grp {
  163. + fsl,pins = <
  164. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  165. + >;
  166. + };
  167. +
  168. + pinctrl_pwm3: pwm3grp {
  169. + fsl,pins = <
  170. + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  171. + >;
  172. + };
  173. +
  174. pinctrl_pwm4: pwm4grp {
  175. fsl,pins = <
  176. MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
  177. --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
  178. +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
  179. @@ -198,6 +198,18 @@
  180. status = "okay";
  181. };
  182. +&pwm2 {
  183. + pinctrl-names = "default";
  184. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  185. + status = "disabled";
  186. +};
  187. +
  188. +&pwm3 {
  189. + pinctrl-names = "default";
  190. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  191. + status = "disabled";
  192. +};
  193. +
  194. &ssi1 {
  195. status = "okay";
  196. };
  197. @@ -290,6 +302,18 @@
  198. >;
  199. };
  200. + pinctrl_pwm2: pwm2grp {
  201. + fsl,pins = <
  202. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  203. + >;
  204. + };
  205. +
  206. + pinctrl_pwm3: pwm3grp {
  207. + fsl,pins = <
  208. + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
  209. + >;
  210. + };
  211. +
  212. pinctrl_uart2: uart2grp {
  213. fsl,pins = <
  214. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
  215. --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
  216. +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
  217. @@ -164,6 +164,18 @@
  218. status = "okay";
  219. };
  220. +&pwm2 {
  221. + pinctrl-names = "default";
  222. + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
  223. + status = "disabled";
  224. +};
  225. +
  226. +&pwm3 {
  227. + pinctrl-names = "default";
  228. + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
  229. + status = "disabled";
  230. +};
  231. +
  232. &uart2 {
  233. pinctrl-names = "default";
  234. pinctrl-0 = <&pinctrl_uart2>;
  235. @@ -242,6 +254,18 @@
  236. >;
  237. };
  238. + pinctrl_pwm2: pwm2grp {
  239. + fsl,pins = <
  240. + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
  241. + >;
  242. + };
  243. +
  244. + pinctrl_pwm3: pwm3grp {
  245. + fsl,pins = <
  246. + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
  247. + >;
  248. + };
  249. +
  250. pinctrl_uart2: uart2grp {
  251. fsl,pins = <
  252. MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1