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037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch

037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch 2.1 KB
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  1. From d86b202436b6f3111c4c37b8701daa0764d2ca55 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Tim Harvey <tharvey@gateworks.com>
    3. 

  3. Date: Thu, 5 Nov 2015 11:10:00 -0800
    4. 

  4. Subject: [PATCH 3/3] ARM: dts: imx: ventana: Allow HDMI and LVDS to work
    5. 

  5.  simultaneously
    6. 

  6. 

  7. Currently it is not possible to have HDMI and LVDS working simultaneously,
    8. 

  8. because both ports try to use PLL5.
    9. 

  9. 

  10. Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
    11. 

  11. driven from independent sources.
    12. 

  12. 

  13. With this change the LDB pixel clock goes to 68.57 MHz, which is still
    14. 

  14. within the valid range for the displays supported by the Ventana boards.
    15. 

  15. 

  16. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
    17. 

  17. ---
    18. 

  18.  arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 7 +++++++
    19. 

  19.  arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 7 +++++++
    20. 

  20.  arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 7 +++++++
    21. 

  21.  3 files changed, 21 insertions(+)
    22. 

  22. 

  23. --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
    24. 

  24. +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
    25. 

  25. @@ -151,6 +151,13 @@
    26. 

  26.  	status = "okay";
    27. 

  27.  };
    28. 

  28.  
    29. 

  29. +&clks {
    30. 

  30. +	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
    31. 

  31. +	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
    32. 

  32. +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
    33. 

  33. +	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
    34. 

  34. +};
    35. 

  35. +
    36. 

  36.  &fec {
    37. 

  37.  	pinctrl-names = "default";
    38. 

  38.  	pinctrl-0 = <&pinctrl_enet>;
    39. 

  39. --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
    40. 

  40. +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
    41. 

  41. @@ -152,6 +152,13 @@
    42. 

  42.  	status = "okay";
    43. 

  43.  };
    44. 

  44.  
    45. 

  45. +&clks {
    46. 

  46. +	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
    47. 

  47. +	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
    48. 

  48. +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
    49. 

  49. +	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
    50. 

  50. +};
    51. 

  51. +
    52. 

  52.  &fec {
    53. 

  53.  	pinctrl-names = "default";
    54. 

  54.  	pinctrl-0 = <&pinctrl_enet>;
    55. 

  55. --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
    56. 

  56. +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
    57. 

  57. @@ -142,6 +142,13 @@
    58. 

  58.  	status = "okay";
    59. 

  59.  };
    60. 

  60.  
    61. 

  61. +&clks {
    62. 

  62. +	assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
    63. 

  63. +	                  <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
    64. 

  64. +	assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
    65. 

  65. +	                  <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
    66. 

  66. +};
    67. 

  67. +
    68. 

  68.  &fec {
    69. 

  69.  	pinctrl-names = "default";
    70. 

  70.  	pinctrl-0 = <&pinctrl_enet>;
    71.