0263-clk-bcm2835-add-missing-osc-and-per-clocks.patch 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184
  1. From 45ef8c48a9c0d695fb649f5188e244fe75672244 Mon Sep 17 00:00:00 2001
  2. From: Martin Sperl <kernel@martin.sperl.org>
  3. Date: Mon, 29 Feb 2016 15:43:57 +0000
  4. Subject: [PATCH] clk: bcm2835: add missing osc and per clocks
  5. Add AVE0, DFT, GP0, GP1, GP2, SLIM, SMI, TEC, DPI, CAM0, CAM1, DSI0E,
  6. and DSI1E. PULSE is not added because it has an extra divider.
  7. Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  8. Signed-off-by: Eric Anholt <eric@anholt.net>
  9. Reviewed-by: Eric Anholt <eric@anholt.net>
  10. (cherry picked from commit d3d6f15fd376e3dbba851724057b112558c70b79)
  11. ---
  12. drivers/clk/bcm/clk-bcm2835.c | 90 +++++++++++++++++++++++++++++++++++++
  13. include/dt-bindings/clock/bcm2835.h | 14 ++++++
  14. 2 files changed, 104 insertions(+)
  15. --- a/drivers/clk/bcm/clk-bcm2835.c
  16. +++ b/drivers/clk/bcm/clk-bcm2835.c
  17. @@ -117,6 +117,8 @@
  18. #define CM_SDCCTL 0x1a8
  19. #define CM_SDCDIV 0x1ac
  20. #define CM_ARMCTL 0x1b0
  21. +#define CM_AVEOCTL 0x1b8
  22. +#define CM_AVEODIV 0x1bc
  23. #define CM_EMMCCTL 0x1c0
  24. #define CM_EMMCDIV 0x1c4
  25. @@ -1618,6 +1620,12 @@ static const struct bcm2835_clk_desc clk
  26. .div_reg = CM_TSENSDIV,
  27. .int_bits = 5,
  28. .frac_bits = 0),
  29. + [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
  30. + .name = "tec",
  31. + .ctl_reg = CM_TECCTL,
  32. + .div_reg = CM_TECDIV,
  33. + .int_bits = 6,
  34. + .frac_bits = 0),
  35. /* clocks with vpu parent mux */
  36. [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
  37. @@ -1632,6 +1640,7 @@ static const struct bcm2835_clk_desc clk
  38. .div_reg = CM_ISPDIV,
  39. .int_bits = 4,
  40. .frac_bits = 8),
  41. +
  42. /*
  43. * Secondary SDRAM clock. Used for low-voltage modes when the PLL
  44. * in the SDRAM controller can't be used.
  45. @@ -1663,6 +1672,36 @@ static const struct bcm2835_clk_desc clk
  46. .is_vpu_clock = true),
  47. /* clocks with per parent mux */
  48. + [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
  49. + .name = "aveo",
  50. + .ctl_reg = CM_AVEOCTL,
  51. + .div_reg = CM_AVEODIV,
  52. + .int_bits = 4,
  53. + .frac_bits = 0),
  54. + [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
  55. + .name = "cam0",
  56. + .ctl_reg = CM_CAM0CTL,
  57. + .div_reg = CM_CAM0DIV,
  58. + .int_bits = 4,
  59. + .frac_bits = 8),
  60. + [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
  61. + .name = "cam1",
  62. + .ctl_reg = CM_CAM1CTL,
  63. + .div_reg = CM_CAM1DIV,
  64. + .int_bits = 4,
  65. + .frac_bits = 8),
  66. + [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
  67. + .name = "dft",
  68. + .ctl_reg = CM_DFTCTL,
  69. + .div_reg = CM_DFTDIV,
  70. + .int_bits = 5,
  71. + .frac_bits = 0),
  72. + [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
  73. + .name = "dpi",
  74. + .ctl_reg = CM_DPICTL,
  75. + .div_reg = CM_DPIDIV,
  76. + .int_bits = 4,
  77. + .frac_bits = 8),
  78. /* Arasan EMMC clock */
  79. [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
  80. @@ -1671,6 +1710,29 @@ static const struct bcm2835_clk_desc clk
  81. .div_reg = CM_EMMCDIV,
  82. .int_bits = 4,
  83. .frac_bits = 8),
  84. +
  85. + /* General purpose (GPIO) clocks */
  86. + [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
  87. + .name = "gp0",
  88. + .ctl_reg = CM_GP0CTL,
  89. + .div_reg = CM_GP0DIV,
  90. + .int_bits = 12,
  91. + .frac_bits = 12,
  92. + .is_mash_clock = true),
  93. + [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
  94. + .name = "gp1",
  95. + .ctl_reg = CM_GP1CTL,
  96. + .div_reg = CM_GP1DIV,
  97. + .int_bits = 12,
  98. + .frac_bits = 12,
  99. + .is_mash_clock = true),
  100. + [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
  101. + .name = "gp2",
  102. + .ctl_reg = CM_GP2CTL,
  103. + .div_reg = CM_GP2DIV,
  104. + .int_bits = 12,
  105. + .frac_bits = 12),
  106. +
  107. /* HDMI state machine */
  108. [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
  109. .name = "hsm",
  110. @@ -1692,12 +1754,26 @@ static const struct bcm2835_clk_desc clk
  111. .int_bits = 12,
  112. .frac_bits = 12,
  113. .is_mash_clock = true),
  114. + [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
  115. + .name = "slim",
  116. + .ctl_reg = CM_SLIMCTL,
  117. + .div_reg = CM_SLIMDIV,
  118. + .int_bits = 12,
  119. + .frac_bits = 12,
  120. + .is_mash_clock = true),
  121. + [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
  122. + .name = "smi",
  123. + .ctl_reg = CM_SMICTL,
  124. + .div_reg = CM_SMIDIV,
  125. + .int_bits = 4,
  126. + .frac_bits = 8),
  127. [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
  128. .name = "uart",
  129. .ctl_reg = CM_UARTCTL,
  130. .div_reg = CM_UARTDIV,
  131. .int_bits = 10,
  132. .frac_bits = 12),
  133. +
  134. /* TV encoder clock. Only operating frequency is 108Mhz. */
  135. [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
  136. .name = "vec",
  137. @@ -1706,6 +1782,20 @@ static const struct bcm2835_clk_desc clk
  138. .int_bits = 4,
  139. .frac_bits = 0),
  140. + /* dsi clocks */
  141. + [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
  142. + .name = "dsi0e",
  143. + .ctl_reg = CM_DSI0ECTL,
  144. + .div_reg = CM_DSI0EDIV,
  145. + .int_bits = 4,
  146. + .frac_bits = 8),
  147. + [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
  148. + .name = "dsi1e",
  149. + .ctl_reg = CM_DSI1ECTL,
  150. + .div_reg = CM_DSI1EDIV,
  151. + .int_bits = 4,
  152. + .frac_bits = 8),
  153. +
  154. /* the gates */
  155. /*
  156. --- a/include/dt-bindings/clock/bcm2835.h
  157. +++ b/include/dt-bindings/clock/bcm2835.h
  158. @@ -50,3 +50,17 @@
  159. #define BCM2835_PLLA_CCP2 33
  160. #define BCM2835_PLLD_DSI0 34
  161. #define BCM2835_PLLD_DSI1 35
  162. +
  163. +#define BCM2835_CLOCK_AVEO 36
  164. +#define BCM2835_CLOCK_DFT 37
  165. +#define BCM2835_CLOCK_GP0 38
  166. +#define BCM2835_CLOCK_GP1 39
  167. +#define BCM2835_CLOCK_GP2 40
  168. +#define BCM2835_CLOCK_SLIM 41
  169. +#define BCM2835_CLOCK_SMI 42
  170. +#define BCM2835_CLOCK_TEC 43
  171. +#define BCM2835_CLOCK_DPI 44
  172. +#define BCM2835_CLOCK_CAM0 45
  173. +#define BCM2835_CLOCK_CAM1 46
  174. +#define BCM2835_CLOCK_DSI0E 47
  175. +#define BCM2835_CLOCK_DSI1E 48