apm82181.dtsi 13 KB

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  1. /*
  2. * Device Tree for Bluestone (APM821xx) board.
  3. *
  4. * Copyright (c) 2010, Applied Micro Circuits Corporation
  5. * Author: Tirumala R Marri <tmarri@apm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. *
  22. */
  23. #include <dt-bindings/input/input.h>
  24. #include <dt-bindings/interrupt-controller/irq.h>
  25. #include <dt-bindings/gpio/gpio.h>
  26. / {
  27. #address-cells = <2>;
  28. #size-cells = <1>;
  29. dcr-parent = <&{/cpus/cpu@0}>;
  30. compatible = "apm,bluestone";
  31. aliases {
  32. ethernet0 = &EMAC0;
  33. };
  34. cpus {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. CPU00: cpu@0 {
  38. device_type = "cpu";
  39. model = "PowerPC,apm82181";
  40. reg = <0x00000000>;
  41. clock-frequency = <0>; /* Filled in by U-Boot */
  42. timebase-frequency = <0>; /* Filled in by U-Boot */
  43. i-cache-line-size = <32>;
  44. d-cache-line-size = <32>;
  45. i-cache-size = <32768>;
  46. d-cache-size = <32768>;
  47. dcr-controller;
  48. dcr-access-method = "native";
  49. next-level-cache = <&L2C0>;
  50. };
  51. };
  52. memory {
  53. device_type = "memory";
  54. reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
  55. };
  56. UIC0: interrupt-controller0 {
  57. compatible = "apm,uic-apm82181","ibm,uic";
  58. interrupt-controller;
  59. cell-index = <0>;
  60. dcr-reg = <0x0c0 0x009>;
  61. #address-cells = <0>;
  62. #size-cells = <0>;
  63. #interrupt-cells = <2>;
  64. };
  65. UIC1: interrupt-controller1 {
  66. compatible = "apm,uic-apm82181","ibm,uic";
  67. interrupt-controller;
  68. cell-index = <1>;
  69. dcr-reg = <0x0d0 0x009>;
  70. #address-cells = <0>;
  71. #size-cells = <0>;
  72. #interrupt-cells = <2>;
  73. interrupts = <0x1e IRQ_TYPE_LEVEL_HIGH
  74. 0x1f IRQ_TYPE_LEVEL_HIGH>; /* cascade */
  75. interrupt-parent = <&UIC0>;
  76. };
  77. UIC2: interrupt-controller2 {
  78. compatible = "apm,uic-apm82181","ibm,uic";
  79. interrupt-controller;
  80. cell-index = <2>;
  81. dcr-reg = <0x0e0 0x009>;
  82. #address-cells = <0>;
  83. #size-cells = <0>;
  84. #interrupt-cells = <2>;
  85. interrupts = <0x0a IRQ_TYPE_LEVEL_HIGH
  86. 0x0b IRQ_TYPE_LEVEL_HIGH>; /* cascade */
  87. interrupt-parent = <&UIC0>;
  88. };
  89. UIC3: interrupt-controller3 {
  90. compatible = "apm,uic-apm82181","ibm,uic";
  91. interrupt-controller;
  92. cell-index = <3>;
  93. dcr-reg = <0x0f0 0x009>;
  94. #address-cells = <0>;
  95. #size-cells = <0>;
  96. #interrupt-cells = <2>;
  97. interrupts = <0x10 IRQ_TYPE_LEVEL_HIGH
  98. 0x11 IRQ_TYPE_LEVEL_HIGH>; /* cascade */
  99. interrupt-parent = <&UIC0>;
  100. };
  101. OCM1: ocm@400040000 {
  102. compatible = "apm,ocm-apm82181", "ibm,ocm";
  103. status = "okay";
  104. cell-index = <1>;
  105. /* configured in U-Boot */
  106. reg = <4 0x00040000 0x8000>; /* 32K */
  107. };
  108. SDR0: sdr {
  109. compatible = "apm,sdr-apm82181", "ibm,sdr-460ex";
  110. dcr-reg = <0x00e 0x002>;
  111. };
  112. CPR0: cpr {
  113. compatible = "apm,cpr-apm82181", "ibm,cpr-460ex";
  114. dcr-reg = <0x00c 0x002>;
  115. };
  116. L2C0: l2c {
  117. compatible = "ibm,l2-cache-apm82181", "ibm,l2-cache";
  118. dcr-reg = <0x020 0x008
  119. 0x030 0x008>;
  120. cache-line-size = <32>;
  121. cache-size = <262144>;
  122. interrupt-parent = <&UIC1>;
  123. interrupts = <0x0b IRQ_TYPE_EDGE_RISING>;
  124. };
  125. CPM0: cpm {
  126. compatible = "ibm,cpm-apm821xx", "ibm,cpm";
  127. cell-index = <0>;
  128. dcr-reg = <0x160 0x003>;
  129. pm-cpu = <0x02000000>;
  130. pm-doze = <0x302570F0>;
  131. pm-nap = <0x302570F0>;
  132. pm-deepsleep = <0x302570F0>;
  133. pm-iic-device = <&IIC0>;
  134. pm-emac-device = <&EMAC0>;
  135. unused-units = <0x00000100>;
  136. idle-doze = <0x02000000>;
  137. standby = <0xfeff791d>;
  138. };
  139. plb {
  140. compatible = "apm,plb-apm82181", "ibm,plb-460ex", "ibm,plb4";
  141. #address-cells = <2>;
  142. #size-cells = <1>;
  143. ranges;
  144. clock-frequency = <0>; /* Filled in by U-Boot */
  145. SDRAM0: sdram {
  146. compatible = "apm,sdram-apm82181", "ibm,sdram-460ex", "ibm,sdram-405gp";
  147. dcr-reg = <0x010 0x002>;
  148. };
  149. RTC: rtc {
  150. compatible = "ibm,rtc";
  151. dcr-reg = <0x240 0x009>;
  152. interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
  153. interrupt-parent = <&UIC2>;
  154. };
  155. CRYPTO: crypto@180000 {
  156. compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
  157. reg = <4 0x00180000 0x80400>;
  158. interrupt-parent = <&UIC0>;
  159. interrupts = <0x1d IRQ_TYPE_LEVEL_HIGH>;
  160. status = "disabled";
  161. };
  162. PKA: pka@114000 {
  163. device_type = "pka";
  164. compatible = "ppc4xx-pka", "amcc,ppc4xx-pka", "amcc, ppc4xx-pka";
  165. reg = <4 0x00114000 0x4000>;
  166. interrupt-parent = <&UIC0>;
  167. interrupts = <0x14 IRQ_TYPE_EDGE_RISING>;
  168. status = "disabled";
  169. };
  170. TRNG: trng@110000 {
  171. device_type = "trng";
  172. compatible = "amcc,ppc460ex-rng", "ppc4xx-rng", "amcc, ppc4xx-trng";
  173. reg = <4 0x00110000 0x100>;
  174. interrupt-parent = <&UIC1>;
  175. interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
  176. status = "disabled";
  177. };
  178. MAL0: mcmal {
  179. compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
  180. descriptor-memory = "ocm";
  181. dcr-reg = <0x180 0x062>;
  182. num-tx-chans = <1>;
  183. num-rx-chans = <1>;
  184. #address-cells = <0>;
  185. #size-cells = <0>;
  186. interrupt-parent = <&UIC2>;
  187. interrupts = < 0x06 IRQ_TYPE_LEVEL_HIGH /*TXEOB*/
  188. 0x07 IRQ_TYPE_LEVEL_HIGH /*RXEOB*/
  189. 0x03 IRQ_TYPE_LEVEL_HIGH /*SERR*/
  190. 0x04 IRQ_TYPE_LEVEL_HIGH /*TXDE*/
  191. 0x05 IRQ_TYPE_LEVEL_HIGH /*RXDE*/
  192. 0x08 IRQ_TYPE_EDGE_FALLING /*TX0 COAL*/
  193. /*0x09 IRQ_TYPE_EDGE_FALLING TX1 COAL*/
  194. 0x0c IRQ_TYPE_EDGE_FALLING /*RX0 COAL*/
  195. /*0x0d IRQ_TYPE_EDGE_FALLING RX1 COAL*/>;
  196. };
  197. AHBDMA0: dma@bffd0800 {
  198. compatible = "snps,dma-spear1340";
  199. reg = <4 0xbffd0800 0x400>;
  200. interrupt-parent = <&UIC0>;
  201. interrupts = <0x19 IRQ_TYPE_LEVEL_HIGH>;
  202. #dma-cells = <3>;
  203. /* use autoconfiguration for the dma setup */
  204. };
  205. SATA0: sata@bffd1000 {
  206. compatible = "amcc,sata-460ex";
  207. reg = <4 0xbffd1000 0x800>;
  208. interrupt-parent = <&UIC0>;
  209. interrupts = <0x1a IRQ_TYPE_LEVEL_HIGH>;
  210. dmas = <&AHBDMA0 0 0 1>;
  211. dma-names = "sata-dma";
  212. status = "disabled";
  213. };
  214. SATA1: sata@bffd1800 {
  215. compatible = "amcc,sata-460ex";
  216. reg = <4 0xbffd1800 0x800>;
  217. interrupt-parent = <&UIC0>;
  218. interrupts = <0x1b IRQ_TYPE_LEVEL_HIGH>;
  219. dmas = <&AHBDMA0 1 0 2>;
  220. dma-names = "sata-dma";
  221. status = "disabled";
  222. };
  223. USBOTG0: usbotg@bff80000 {
  224. compatible = "amcc,usb-otg-405ex";
  225. reg = <4 0xbff80000 0x10000>;
  226. interrupt-parent = <&USBOTG0>;
  227. interrupts = <0 1 2>;
  228. #interrupt-cells = <1>;
  229. #address-cells = <0>;
  230. #size-cells = <0>;
  231. interrupt-map = <0 &UIC2 0x1c IRQ_TYPE_LEVEL_HIGH /* USB-OTG */
  232. 1 &UIC1 0x1a IRQ_TYPE_LEVEL_LOW /* HIGH-POWER */
  233. 2 &UIC0 0x0c IRQ_TYPE_LEVEL_HIGH /* DMA */>;
  234. dr_mode = "host";
  235. status = "disabled";
  236. };
  237. POB0: opb {
  238. compatible = "ibm,opb-460ex", "ibm,opb";
  239. #address-cells = <1>;
  240. #size-cells = <1>;
  241. ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
  242. clock-frequency = <0>; /* Filled in by U-Boot */
  243. EBC0: ebc {
  244. compatible = "ibm,ebc-460ex", "ibm,ebc";
  245. dcr-reg = <0x012 0x002>;
  246. #address-cells = <2>;
  247. #size-cells = <1>;
  248. clock-frequency = <0>; /* Filled in by U-Boot */
  249. /* ranges property is supplied by U-Boot */
  250. ranges = <0x00000003 0x00000000 0xe0000000 0x8000000>;
  251. interrupts = <0x06 IRQ_TYPE_LEVEL_HIGH>;
  252. interrupt-parent = <&UIC1>;
  253. nor_flash@0,0 {
  254. compatible = "cfi-flash";
  255. bank-width = <1>;
  256. reg = <0x00000000 0x00000000 0x00100000>;
  257. #address-cells = <1>;
  258. #size-cells = <1>;
  259. status = "disabled";
  260. };
  261. ndfc@1,0 {
  262. compatible = "ibm,ndfc";
  263. reg = <00000003 00000000 00002000>;
  264. ccr = <0x00001000>;
  265. bank-settings = <0x80002222>;
  266. #address-cells = <1>;
  267. #size-cells = <1>;
  268. status = "disabled";
  269. nand {
  270. #address-cells = <1>;
  271. #size-cells = <1>;
  272. };
  273. };
  274. };
  275. UART0: serial@ef600300 {
  276. device_type = "serial";
  277. compatible = "ns16550";
  278. reg = <0xef600300 0x00000008>;
  279. virtual-reg = <0xef600300>;
  280. clock-frequency = <0>; /* Filled in by U-Boot */
  281. current-speed = <0>; /* Filled in by U-Boot */
  282. interrupt-parent = <&UIC1>;
  283. interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
  284. status = "disabled";
  285. };
  286. UART1: serial@ef600400 {
  287. device_type = "serial";
  288. compatible = "ns16550";
  289. reg = <0xef600400 0x00000008>;
  290. virtual-reg = <0xef600400>;
  291. clock-frequency = <0>; /* Filled in by U-Boot */
  292. current-speed = <0>; /* Filled in by U-Boot */
  293. interrupt-parent = <&UIC0>;
  294. interrupts = <0x01 IRQ_TYPE_LEVEL_HIGH>;
  295. status = "disabled";
  296. };
  297. GPIO0: gpio@ef600b00 {
  298. compatible = "ibm,ppc4xx-gpio";
  299. reg = <0xef600b00 0x00000048>;
  300. #gpio-cells = <2>;
  301. gpio-controller;
  302. status = "disabled";
  303. };
  304. IIC0: i2c@ef600700 {
  305. compatible = "ibm,iic-460ex", "ibm,iic";
  306. reg = <0xef600700 0x00000014>;
  307. interrupt-parent = <&UIC0>;
  308. interrupts = <0x02 IRQ_TYPE_LEVEL_HIGH>;
  309. #address-cells = <1>;
  310. #size-cells = <0>;
  311. status = "disabled";
  312. };
  313. IIC1: i2c@ef600800 {
  314. compatible = "ibm,iic-460ex", "ibm,iic";
  315. reg = <0xef600800 0x00000014>;
  316. interrupt-parent = <&UIC0>;
  317. interrupts = <0x03 IRQ_TYPE_LEVEL_HIGH>;
  318. status = "disabled";
  319. };
  320. RGMII0: emac-rgmii@ef601500 {
  321. compatible = "ibm,rgmii-405ex", "ibm,rgmii";
  322. reg = <0xef601500 0x00000008>;
  323. has-mdio;
  324. };
  325. TAH0: emac-tah@ef601350 {
  326. compatible = "ibm,tah-460ex", "ibm,tah";
  327. reg = <0xef601350 0x00000030>;
  328. };
  329. EMAC0: ethernet@ef600c00 {
  330. device_type = "network";
  331. compatible = "ibm,emac-apm821xx", "ibm,emac4sync";
  332. interrupt-parent = <&EMAC0>;
  333. interrupts = <0 1>;
  334. #interrupt-cells = <1>;
  335. #address-cells = <0>;
  336. #size-cells = <0>;
  337. interrupt-map = <0 &UIC2 0x10 IRQ_TYPE_LEVEL_HIGH /* Status */
  338. 1 &UIC2 0x14 IRQ_TYPE_LEVEL_HIGH /* Wake */>;
  339. reg = <0xef600c00 0x000000c4>;
  340. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  341. mal-device = <&MAL0>;
  342. mal-tx-channel = <0>;
  343. mal-rx-channel = <0>;
  344. cell-index = <0>;
  345. max-frame-size = <9000>;
  346. rx-fifo-size = <16384>;
  347. tx-fifo-size = <2048>;
  348. fifo-entry-size = <10>;
  349. phy-mode = "rgmii";
  350. phy-map = <0x00000000>;
  351. rgmii-device = <&RGMII0>;
  352. rgmii-channel = <0>;
  353. tah-device = <&TAH0>;
  354. tah-channel = <0>;
  355. has-inverted-stacr-oc;
  356. has-new-stacr-staopc;
  357. status = "disabled";
  358. };
  359. };
  360. PCIE0: pciex@d00000000 {
  361. device_type = "pci";
  362. #interrupt-cells = <1>;
  363. #size-cells = <2>;
  364. #address-cells = <3>;
  365. compatible = "ibm,plb-pciex-apm821xx", "ibm,plb-pciex";
  366. primary;
  367. port = <0x0>; /* port number */
  368. reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
  369. 0x0000000c 0x08010000 0x00001000>; /* Registers */
  370. dcr-reg = <0x100 0x020>;
  371. sdr-base = <0x300>;
  372. /* Outbound ranges, one memory and one IO,
  373. * later cannot be changed
  374. */
  375. ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
  376. 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
  377. 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
  378. /* Inbound 2GB range starting at 0 */
  379. dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
  380. /* This drives busses 0x40 to 0x7f */
  381. bus-range = <0x40 0x7f>;
  382. /* Legacy interrupts (note the weird polarity, the bridge seems
  383. * to invert PCIe legacy interrupts).
  384. * We are de-swizzling here because the numbers are actually for
  385. * port of the root complex virtual P2P bridge. But I want
  386. * to avoid putting a node for it in the tree, so the numbers
  387. * below are basically de-swizzled numbers.
  388. * The real slot is on idsel 0, so the swizzling is 1:1
  389. */
  390. interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  391. interrupt-map = <
  392. 0x0 0x0 0x0 0x1 &UIC3 0x0c IRQ_TYPE_LEVEL_HIGH /* swizzled int A */
  393. 0x0 0x0 0x0 0x2 &UIC3 0x0d IRQ_TYPE_LEVEL_HIGH /* swizzled int B */
  394. 0x0 0x0 0x0 0x3 &UIC3 0x0e IRQ_TYPE_LEVEL_HIGH /* swizzled int C */
  395. 0x0 0x0 0x0 0x4 &UIC3 0x0f IRQ_TYPE_LEVEL_HIGH /* swizzled int D */>;
  396. status = "disabled";
  397. };
  398. MSI: ppc4xx-msi@C10000000 {
  399. compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
  400. reg = < 0xC 0x10000000 0x100
  401. 0xC 0x10000000 0x100>;
  402. sdr-base = <0x36C>;
  403. msi-data = <0x00004440>;
  404. msi-mask = <0x0000ffe0>;
  405. interrupts =<0 1 2 3 4 5 6 7>;
  406. interrupt-parent = <&MSI>;
  407. #interrupt-cells = <1>;
  408. #address-cells = <0>;
  409. #size-cells = <0>;
  410. msi-available-ranges = <0x0 0x100>;
  411. interrupt-map = <
  412. 0 &UIC3 0x18 IRQ_TYPE_EDGE_RISING
  413. 1 &UIC3 0x19 IRQ_TYPE_EDGE_RISING
  414. 2 &UIC3 0x1a IRQ_TYPE_EDGE_RISING
  415. 3 &UIC3 0x1b IRQ_TYPE_EDGE_RISING
  416. 4 &UIC3 0x1c IRQ_TYPE_EDGE_RISING
  417. 5 &UIC3 0x1d IRQ_TYPE_EDGE_RISING
  418. 6 &UIC3 0x1e IRQ_TYPE_EDGE_RISING
  419. 7 &UIC3 0x1f IRQ_TYPE_EDGE_RISING
  420. >;
  421. status = "disabled";
  422. };
  423. };
  424. };