ArcherC50.dts 2.9 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/input/input.h>
  3. #include <dt-bindings/gpio/gpio.h>
  4. #include "mt7620a.dtsi"
  5. / {
  6. compatible = "ralink,mt7620a-soc";
  7. model = "TP-Link Archer C50";
  8. chosen {
  9. bootargs = "console=ttyS0,115200";
  10. };
  11. gpio-leds {
  12. compatible = "gpio-leds";
  13. lan {
  14. label = "c50:green:lan";
  15. gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  16. };
  17. power {
  18. label = "c50:green:power";
  19. gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  20. default-state = "on";
  21. };
  22. usb {
  23. label = "c50:green:usb";
  24. gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
  25. };
  26. wan {
  27. label = "c50:green:wan";
  28. gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
  29. };
  30. wan_orange {
  31. label = "c50:orange:wan";
  32. gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
  33. };
  34. wlan5g {
  35. label = "c50:green:wlan5g";
  36. gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  37. };
  38. wlan2g {
  39. label = "c50:green:wlan2g";
  40. gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
  41. };
  42. wps {
  43. label = "c50:green:wps";
  44. gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  45. };
  46. };
  47. gpio-keys-polled {
  48. compatible = "gpio-keys-polled";
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. poll-interval = <20>;
  52. reset {
  53. label = "reset";
  54. gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  55. linux,code = <KEY_RESTART>;
  56. };
  57. rfkill {
  58. label = "rfkill";
  59. gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  60. linux,code = <KEY_RFKILL>;
  61. }; };
  62. };
  63. &gpio1 {
  64. status = "okay";
  65. };
  66. &gpio2 {
  67. status = "okay";
  68. };
  69. &gpio3 {
  70. status = "okay";
  71. };
  72. &spi0 {
  73. status = "okay";
  74. m25p80@0 {
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. compatible = "jedec,spi-nor";
  78. reg = <0>;
  79. spi-max-frequency = <10000000>;
  80. partition@0 {
  81. label = "u-boot";
  82. reg = <0x0 0x20000>;
  83. read-only;
  84. };
  85. partition@20000 {
  86. label = "firmware";
  87. reg = <0x20000 0x7a0000>;
  88. };
  89. partition@7c0000 {
  90. label = "config";
  91. reg = <0x7c0000 0x10000>;
  92. read-only;
  93. };
  94. rom: partition@7d0000 {
  95. label = "rom";
  96. reg = <0x7d0000 0x10000>;
  97. read-only;
  98. };
  99. partition@7e0000 {
  100. label = "romfile";
  101. reg = <0x7e0000 0x10000>;
  102. read-only;
  103. };
  104. radio: partition@7f0000 {
  105. label = "radio";
  106. reg = <0x7f0000 0x10000>;
  107. read-only;
  108. };
  109. };
  110. };
  111. &pinctrl {
  112. state_default: pinctrl0 {
  113. gpio {
  114. ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "ephy", "spi refclk", "mdio", "wdt", "nd_sd";
  115. ralink,function = "gpio";
  116. };
  117. pa {
  118. ralink,group = "pa";
  119. ralink,function = "pa";
  120. };
  121. };
  122. };
  123. &ethernet {
  124. pinctrl-names = "default";
  125. mtd-mac-address = <&rom 0xf100>;
  126. mediatek,portmap = "wllll";
  127. };
  128. &ehci {
  129. status = "okay";
  130. };
  131. &ohci {
  132. status = "okay";
  133. };
  134. &gsw {
  135. mediatek,port4 = "ephy";
  136. };
  137. &wmac {
  138. ralink,mtd-eeprom = <&radio 0>;
  139. mtd-mac-address = <&rom 0xf100>;
  140. mtd-mac-address-increment = <(-2)>;
  141. };
  142. &pcie {
  143. status = "okay";
  144. pcie-bridge {
  145. mt76@0,0 {
  146. reg = <0x0000 0 0 0 0>;
  147. device_type = "pci";
  148. mediatek,mtd-eeprom = <&radio 32768>;
  149. ieee80211-freq-limit = <5000000 6000000>;
  150. mtd-mac-address = <&rom 0xf100>;
  151. mtd-mac-address-increment = <(-1)>;
  152. };
  153. };
  154. };