1097-mtd-fsl-quadspi-use-the-property-fields-of-SPI-NOR.patch 2.7 KB

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  1. From 5c315652c1b43a6a3abe48c2842cde822ac0ff3c Mon Sep 17 00:00:00 2001
  2. From: Yunhui Cui <B56489@freescale.com>
  3. Date: Wed, 20 Jan 2016 18:40:31 +0800
  4. Subject: [PATCH 097/113] mtd:fsl-quadspi:use the property fields of SPI-NOR
  5. We can get the read/write/erase opcode from the spi nor framework
  6. directly. This patch uses the information stored in the SPI-NOR to
  7. remove the hardcode in the fsl_qspi_init_lut().
  8. Signed-off-by: Yunhui Cui <B56489@freescale.com>
  9. ---
  10. drivers/mtd/spi-nor/fsl-quadspi.c | 40 +++++++++++--------------------------
  11. 1 file changed, 12 insertions(+), 28 deletions(-)
  12. --- a/drivers/mtd/spi-nor/fsl-quadspi.c
  13. +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
  14. @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl
  15. void __iomem *base = q->iobase;
  16. int rxfifo = q->devtype_data->rxfifo;
  17. u32 lut_base;
  18. - u8 cmd, addrlen, dummy;
  19. int i;
  20. + struct spi_nor *nor = &q->nor[0];
  21. + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
  22. + u8 read_op = nor->read_opcode;
  23. + u8 read_dm = nor->read_dummy;
  24. +
  25. fsl_qspi_unlock_lut(q);
  26. /* Clear all the LUT table */
  27. @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl
  28. /* Quad Read */
  29. lut_base = SEQID_QUAD_READ * 4;
  30. - if (q->nor_size <= SZ_16M) {
  31. - cmd = SPINOR_OP_READ_1_1_4;
  32. - addrlen = ADDR24BIT;
  33. - dummy = 8;
  34. - } else {
  35. - /* use the 4-byte address */
  36. - cmd = SPINOR_OP_READ_1_1_4;
  37. - addrlen = ADDR32BIT;
  38. - dummy = 8;
  39. - }
  40. -
  41. - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
  42. + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen),
  43. base + QUADSPI_LUT(lut_base));
  44. - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
  45. + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
  46. + LUT1(FSL_READ, PAD4, rxfifo),
  47. base + QUADSPI_LUT(lut_base + 1));
  48. /* Write enable */
  49. @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl
  50. /* Page Program */
  51. lut_base = SEQID_PP * 4;
  52. - if (q->nor_size <= SZ_16M) {
  53. - cmd = SPINOR_OP_PP;
  54. - addrlen = ADDR24BIT;
  55. - } else {
  56. - /* use the 4-byte address */
  57. - cmd = SPINOR_OP_PP;
  58. - addrlen = ADDR32BIT;
  59. - }
  60. -
  61. - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
  62. + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
  63. + LUT1(ADDR, PAD1, addrlen),
  64. base + QUADSPI_LUT(lut_base));
  65. qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
  66. base + QUADSPI_LUT(lut_base + 1));
  67. @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl
  68. /* Erase a sector */
  69. lut_base = SEQID_SE * 4;
  70. - cmd = q->nor[0].erase_opcode;
  71. - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
  72. -
  73. - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
  74. + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
  75. + LUT1(ADDR, PAD1, addrlen),
  76. base + QUADSPI_LUT(lut_base));
  77. /* Erase the whole chip */