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- From ae717a9744a3e18f2ed0a6aa44e279c89ad5052c Mon Sep 17 00:00:00 2001
- From: Gabriele Paoloni <gabriele.paoloni@huawei.com>
- Date: Sat, 16 Apr 2016 12:03:39 +0100
- Subject: [PATCH 59/70] PCI: designware: Remove incorrect RC memory base/limit
- configuration
- Currently dw_pcie_setup_rc() configures memory base and memory limit in the
- type1 configuration header for the root complex. In doing so it uses the
- CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
- This is wrong and it is useless since the configuration is overwritten
- later on when pci_bus_assign_resources() is called.
- Remove this configuration from dw_pcie_setup_rc().
- Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
- Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
- Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
- ---
- drivers/pci/host/pcie-designware.c | 8 --------
- 1 file changed, 8 deletions(-)
- --- a/drivers/pci/host/pcie-designware.c
- +++ b/drivers/pci/host/pcie-designware.c
- @@ -708,8 +708,6 @@ static struct pci_ops dw_pcie_ops = {
- void dw_pcie_setup_rc(struct pcie_port *pp)
- {
- u32 val;
- - u32 membase;
- - u32 memlimit;
-
- /* set the number of lanes */
- dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
- @@ -768,12 +766,6 @@ void dw_pcie_setup_rc(struct pcie_port *
- val |= 0x00010100;
- dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
-
- - /* setup memory base, memory limit */
- - membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
- - memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
- - val = memlimit | membase;
- - dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
- -
- /* setup command register */
- dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
- val &= 0xffff0000;
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