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- From a0a4f406c7e90b2be66e88ea8b21699940c0823f Mon Sep 17 00:00:00 2001
- From: Joao Pinto <Joao.Pinto@synopsys.com>
- Date: Thu, 10 Mar 2016 14:44:44 -0600
- Subject: [PATCH 57/70] PCI: designware: Add default link up check if
- sub-driver doesn't override
- Add a default DesignWare "link_up" test for use when a sub-driver doesn't
- supply its own pcie_host_ops.link_up() method.
- [bhelgaas: changelog, split into its own patch]
- Signed-off-by: Joao Pinto <jpinto@synopsys.com>
- Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
- Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
- ---
- drivers/pci/host/pcie-designware.c | 10 +++++++++-
- 1 file changed, 9 insertions(+), 1 deletion(-)
- --- a/drivers/pci/host/pcie-designware.c
- +++ b/drivers/pci/host/pcie-designware.c
- @@ -70,6 +70,11 @@
- #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
- #define PCIE_ATU_UPPER_TARGET 0x91C
-
- +/* PCIe Port Logic registers */
- +#define PLR_OFFSET 0x700
- +#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
- +#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
- +
- static struct pci_ops dw_pcie_ops;
-
- int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
- @@ -401,10 +406,13 @@ int dw_pcie_wait_for_link(struct pcie_po
-
- int dw_pcie_link_up(struct pcie_port *pp)
- {
- + u32 val;
- +
- if (pp->ops->link_up)
- return pp->ops->link_up(pp);
-
- - return 0;
- + val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
- + return val & PCIE_PHY_DEBUG_R1_LINK_UP;
- }
-
- static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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