bcm6362.dtsi 1.5 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "brcm,bcm6362";
  5. aliases {
  6. gpio0 = &gpio0;
  7. gpio1 = &gpio1;
  8. };
  9. cpus {
  10. #address-cells = <1>;
  11. #size-cells = <0>;
  12. cpu@0 {
  13. compatible = "brcm,bmips4350", "mips,mips4Kc";
  14. device_type = "cpu";
  15. reg = <0>;
  16. };
  17. cpu@1 {
  18. compatible = "brcm,bmips4350", "mips,mips4Kc";
  19. device_type = "cpu";
  20. reg = <1>;
  21. };
  22. };
  23. cpu_intc: interrupt-controller {
  24. #address-cells = <0>;
  25. compatible = "mti,cpu-interrupt-controller";
  26. interrupt-controller;
  27. #interrupt-cells = <1>;
  28. };
  29. memory { device_type = "memory"; reg = <0 0>; };
  30. ubus@10000000 {
  31. #address-cells = <1>;
  32. #size-cells = <1>;
  33. ranges;
  34. compatible = "simple-bus";
  35. ext_intc: interrupt-controller@10000018 {
  36. compatible = "brcm,bcm6345-ext-intc";
  37. reg = <0x10000018 0x4>;
  38. interrupt-controller;
  39. #interrupt-cells = <2>;
  40. interrupt-parent = <&periph_intc>;
  41. interrupts = <40>, <41>, <42>, <43>;
  42. };
  43. periph_intc: interrupt-controller@10000020 {
  44. compatible = "brcm,bcm6345-l1-intc";
  45. reg = <0x10000020 0x10>,
  46. <0x10000030 0x10>;
  47. interrupt-controller;
  48. #interrupt-cells = <1>;
  49. interrupt-parent = <&cpu_intc>;
  50. interrupts = <2>, <3>;
  51. };
  52. gpio1: gpio-controller@10000080 {
  53. compatible = "brcm,bcm6345-gpio";
  54. reg = <0x10000080 4>, <0x10000088 4>;
  55. gpio-controller;
  56. #gpio-cells = <2>;
  57. ngpios = <16>;
  58. };
  59. gpio0: gpio-controller@10000084 {
  60. compatible = "brcm,bcm6345-gpio";
  61. reg = <0x10000084 4>, <0x1000008c 4>;
  62. gpio-controller;
  63. #gpio-cells = <2>;
  64. };
  65. };
  66. };