0485-Overlay-for-Microchip-MCP23S08-17-SPI-gpio-expanders.patch 26 KB

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  1. From 4b90ef9ce4197f9d7c58290d2b13a7a3d06679c5 Mon Sep 17 00:00:00 2001
  2. From: wavelet2 <a3d35232@btinternet.com>
  3. Date: Fri, 19 Aug 2016 09:32:53 +0100
  4. Subject: [PATCH] Overlay for Microchip MCP23S08/17 SPI gpio expanders (#1566)
  5. Added Overlay for Microchip MCP23S08/17 SPI gpio expanders
  6. ---
  7. arch/arm/boot/dts/overlays/Makefile | 1 +
  8. arch/arm/boot/dts/overlays/README | 24 +
  9. arch/arm/boot/dts/overlays/mcp23s17-overlay.dts | 732 ++++++++++++++++++++++++
  10. 3 files changed, 757 insertions(+)
  11. create mode 100644 arch/arm/boot/dts/overlays/mcp23s17-overlay.dts
  12. --- a/arch/arm/boot/dts/overlays/Makefile
  13. +++ b/arch/arm/boot/dts/overlays/Makefile
  14. @@ -49,6 +49,7 @@ dtbo-$(RPI_DT_OVERLAYS) += justboom-dac.
  15. dtbo-$(RPI_DT_OVERLAYS) += justboom-digi.dtbo
  16. dtbo-$(RPI_DT_OVERLAYS) += lirc-rpi.dtbo
  17. dtbo-$(RPI_DT_OVERLAYS) += mcp23017.dtbo
  18. +dtbo-$(RPI_DT_OVERLAYS) += mcp23s17.dtbo
  19. dtbo-$(RPI_DT_OVERLAYS) += mcp2515-can0.dtbo
  20. dtbo-$(RPI_DT_OVERLAYS) += mcp2515-can1.dtbo
  21. dtbo-$(RPI_DT_OVERLAYS) += mmc.dtbo
  22. --- a/arch/arm/boot/dts/overlays/README
  23. +++ b/arch/arm/boot/dts/overlays/README
  24. @@ -628,6 +628,30 @@ Params: gpiopin Gpio pin
  25. addr I2C address of the MCP23017 (default: 0x20)
  26. +Name: mcp23s17
  27. +Info: Configures the MCP23S08/17 SPI GPIO expanders.
  28. + If devices are present on SPI1 or SPI2, those interfaces must be enabled
  29. + with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
  30. + If interrupts are enabled for a device on a given CS# on a SPI bus, that
  31. + device must be the only one present on that SPI bus/CS#.
  32. +Load: dtoverlay=mcp23s17,<param>=<val>
  33. +Params: s08-spi<n>-<m>-present 4-bit integer, bitmap indicating MCP23S08
  34. + devices present on SPI<n>, CS#<m>
  35. +
  36. + s17-spi<n>-<m>-present 8-bit integer, bitmap indicating MCP23S17
  37. + devices present on SPI<n>, CS#<m>
  38. +
  39. + s08-spi<n>-<m>-int-gpio integer, enables interrupts on a single
  40. + MCP23S08 device on SPI<n>, CS#<m>, specifies
  41. + the GPIO pin to which INT output of MCP23S08
  42. + is connected.
  43. +
  44. + s17-spi<n>-<m>-int-gpio integer, enables mirrored interrupts on a
  45. + single MCP23S17 device on SPI<n>, CS#<m>,
  46. + specifies the GPIO pin to which either INTA
  47. + or INTB output of MCP23S17 is connected.
  48. +
  49. +
  50. Name: mcp2515-can0
  51. Info: Configures the MCP2515 CAN controller on spi0.0
  52. Load: dtoverlay=mcp2515-can0,<param>=<val>
  53. --- /dev/null
  54. +++ b/arch/arm/boot/dts/overlays/mcp23s17-overlay.dts
  55. @@ -0,0 +1,732 @@
  56. +// Overlay for MCP23S08/17 GPIO Extenders from Microchip Semiconductor
  57. +
  58. +// dtparams:
  59. +// s08-spi<n>-<m>-present - 4-bit integer, bitmap indicating MCP23S08 devices present on SPI<n>, CS#<m>.
  60. +// s17-spi<n>-<m>-present - 8-bit integer, bitmap indicating MCP23S17 devices present on SPI<n>, CS#<m>.
  61. +// s08-spi<n>-<m>-int-gpio - integer, enables interrupts on a single MCP23S08 device on SPI<n>, CS#<m>, specifies the GPIO pin to which INT output is connected.
  62. +// s17-spi<n>-<m>-int-gpio - integer, enables mirrored interrupts on a single MCP23S17 device on SPI<n>, CS#<m>, specifies the GPIO pin to which either INTA or INTB output is connected.
  63. +//
  64. +// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays.
  65. +// If interrupts are enabled for a device on a given CS# on a SPI bus, that device must be the only one present on that SPI bus/CS#.
  66. +//
  67. +// Example 1: A single MCP23S17 device on SPI0, CS#0 with its SPI addr set to 0 and INTA output connected to GPIO25:
  68. +// dtoverlay=mcp23s17:s17-spi0-0-present=1,s17-spi0-0-int-gpio=25
  69. +//
  70. +// Example 2: Two MCP23S08 devices on SPI1, CS#0 with their addrs set to 2 and 3. Three MCP23S17 devices on SPI1, CS#1 with their addrs set to 0, 1 and 7:
  71. +// dtoverlay=spi1-2cs
  72. +// dtoverlay=mcp23s17:s08-spi1-0-present=12,s17-spi1-1-present=131
  73. +
  74. +/dts-v1/;
  75. +/plugin/;
  76. +
  77. +/ {
  78. + compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709";
  79. +
  80. + // disable spi-dev on spi0.0
  81. + fragment@0 {
  82. + target = <&spidev0>;
  83. + __dormant__ {
  84. + status = "disabled";
  85. + };
  86. + };
  87. +
  88. + // disable spi-dev on spi0.1
  89. + fragment@1 {
  90. + target = <&spidev1>;
  91. + __dormant__ {
  92. + status = "disabled";
  93. + };
  94. + };
  95. +
  96. + // disable spi-dev on spi1.0
  97. + fragment@2 {
  98. + target-path = "spi1/spidev@0";
  99. + __dormant__ {
  100. + status = "disabled";
  101. + };
  102. + };
  103. +
  104. + // disable spi-dev on spi1.1
  105. + fragment@3 {
  106. + target-path = "spi1/spidev@1";
  107. + __dormant__ {
  108. + status = "disabled";
  109. + };
  110. + };
  111. +
  112. + // disable spi-dev on spi1.2
  113. + fragment@4 {
  114. + target-path = "spi1/spidev@2";
  115. + __dormant__ {
  116. + status = "disabled";
  117. + };
  118. + };
  119. +
  120. + // disable spi-dev on spi2.0
  121. + fragment@5 {
  122. + target-path = "spi2/spidev@0";
  123. + __dormant__ {
  124. + status = "disabled";
  125. + };
  126. + };
  127. +
  128. + // disable spi-dev on spi2.1
  129. + fragment@6 {
  130. + target-path = "spi2/spidev@1";
  131. + __dormant__ {
  132. + status = "disabled";
  133. + };
  134. + };
  135. +
  136. + // disable spi-dev on spi2.2
  137. + fragment@7 {
  138. + target-path = "spi2/spidev@2";
  139. + __dormant__ {
  140. + status = "disabled";
  141. + };
  142. + };
  143. +
  144. + // enable one or more mcp23s08s on spi0.0
  145. + fragment@8 {
  146. + target = <&spi0>;
  147. + __dormant__ {
  148. + status = "okay";
  149. + #address-cells = <1>;
  150. + #size-cells = <0>;
  151. + mcp23s08_00: mcp23s08@0 {
  152. + compatible = "microchip,mcp23s08";
  153. + gpio-controller;
  154. + #gpio-cells = <2>;
  155. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi0-0-present parameter */
  156. + reg = <0>;
  157. + spi-max-frequency = <500000>;
  158. + status = "okay";
  159. + #interrupt-cells=<2>;
  160. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi0-0-int-gpio parameter */
  161. + };
  162. + };
  163. + };
  164. +
  165. + // enable one or more mcp23s08s on spi0.1
  166. + fragment@9 {
  167. + target = <&spi0>;
  168. + __dormant__ {
  169. + status = "okay";
  170. + #address-cells = <1>;
  171. + #size-cells = <0>;
  172. + mcp23s08_01: mcp23s08@1 {
  173. + compatible = "microchip,mcp23s08";
  174. + gpio-controller;
  175. + #gpio-cells = <2>;
  176. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi0-1-present parameter */
  177. + reg = <1>;
  178. + spi-max-frequency = <500000>;
  179. + status = "okay";
  180. + #interrupt-cells=<2>;
  181. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi0-1-int-gpio parameter */
  182. + };
  183. + };
  184. + };
  185. +
  186. + // enable one or more mcp23s08s on spi1.0
  187. + fragment@10 {
  188. + target = <&spi1>;
  189. + __dormant__ {
  190. + status = "okay";
  191. + #address-cells = <1>;
  192. + #size-cells = <0>;
  193. + mcp23s08_10: mcp23s08@0 {
  194. + compatible = "microchip,mcp23s08";
  195. + gpio-controller;
  196. + #gpio-cells = <2>;
  197. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi1-0-present parameter */
  198. + reg = <0>;
  199. + spi-max-frequency = <500000>;
  200. + status = "okay";
  201. + #interrupt-cells=<2>;
  202. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi1-0-int-gpio parameter */
  203. + };
  204. + };
  205. + };
  206. +
  207. + // enable one or more mcp23s08s on spi1.1
  208. + fragment@11 {
  209. + target = <&spi1>;
  210. + __dormant__ {
  211. + status = "okay";
  212. + #address-cells = <1>;
  213. + #size-cells = <0>;
  214. + mcp23s08_11: mcp23s08@1 {
  215. + compatible = "microchip,mcp23s08";
  216. + gpio-controller;
  217. + #gpio-cells = <2>;
  218. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi1-1-present parameter */
  219. + reg = <1>;
  220. + spi-max-frequency = <500000>;
  221. + status = "okay";
  222. + #interrupt-cells=<2>;
  223. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi1-1-int-gpio parameter */
  224. + };
  225. + };
  226. + };
  227. +
  228. + // enable one or more mcp23s08s on spi1.2
  229. + fragment@12 {
  230. + target = <&spi1>;
  231. + __dormant__ {
  232. + status = "okay";
  233. + #address-cells = <1>;
  234. + #size-cells = <0>;
  235. + mcp23s08_12: mcp23s08@2 {
  236. + compatible = "microchip,mcp23s08";
  237. + gpio-controller;
  238. + #gpio-cells = <2>;
  239. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi1-2-present parameter */
  240. + reg = <2>;
  241. + spi-max-frequency = <500000>;
  242. + status = "okay";
  243. + #interrupt-cells=<2>;
  244. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi1-2-int-gpio parameter */
  245. + };
  246. + };
  247. + };
  248. +
  249. + // enable one or more mcp23s08s on spi2.0
  250. + fragment@13 {
  251. + target = <&spi2>;
  252. + __dormant__ {
  253. + status = "okay";
  254. + #address-cells = <1>;
  255. + #size-cells = <0>;
  256. + mcp23s08_20: mcp23s08@0 {
  257. + compatible = "microchip,mcp23s08";
  258. + gpio-controller;
  259. + #gpio-cells = <2>;
  260. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi2-0-present parameter */
  261. + reg = <0>;
  262. + spi-max-frequency = <500000>;
  263. + status = "okay";
  264. + #interrupt-cells=<2>;
  265. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi2-0-int-gpio parameter */
  266. + };
  267. + };
  268. + };
  269. +
  270. + // enable one or more mcp23s08s on spi2.1
  271. + fragment@14 {
  272. + target = <&spi2>;
  273. + __dormant__ {
  274. + status = "okay";
  275. + #address-cells = <1>;
  276. + #size-cells = <0>;
  277. + mcp23s08_21: mcp23s08@1 {
  278. + compatible = "microchip,mcp23s08";
  279. + gpio-controller;
  280. + #gpio-cells = <2>;
  281. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi2-1-present parameter */
  282. + reg = <1>;
  283. + spi-max-frequency = <500000>;
  284. + status = "okay";
  285. + #interrupt-cells=<2>;
  286. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi2-1-int-gpio parameter */
  287. + };
  288. + };
  289. + };
  290. +
  291. + // enable one or more mcp23s08s on spi2.2
  292. + fragment@15 {
  293. + target = <&spi2>;
  294. + __dormant__ {
  295. + status = "okay";
  296. + #address-cells = <1>;
  297. + #size-cells = <0>;
  298. + mcp23s08_22: mcp23s08@2 {
  299. + compatible = "microchip,mcp23s08";
  300. + gpio-controller;
  301. + #gpio-cells = <2>;
  302. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s08-spi2-2-present parameter */
  303. + reg = <2>;
  304. + spi-max-frequency = <500000>;
  305. + status = "okay";
  306. + #interrupt-cells=<2>;
  307. + interrupts = <0 2>; /* 1st word overwritten by mcp23s08-spi2-2-int-gpio parameter */
  308. + };
  309. + };
  310. + };
  311. +
  312. + // enable one or more mcp23s17s on spi0.0
  313. + fragment@16 {
  314. + target = <&spi0>;
  315. + __dormant__ {
  316. + status = "okay";
  317. + #address-cells = <1>;
  318. + #size-cells = <0>;
  319. + mcp23s17_00: mcp23s17@0 {
  320. + compatible = "microchip,mcp23s17";
  321. + gpio-controller;
  322. + #gpio-cells = <2>;
  323. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi0-0-present parameter */
  324. + reg = <0>;
  325. + spi-max-frequency = <500000>;
  326. + status = "okay";
  327. + #interrupt-cells=<2>;
  328. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi0-0-int-gpio parameter */
  329. + };
  330. + };
  331. + };
  332. +
  333. + // enable one or more mcp23s17s on spi0.1
  334. + fragment@17 {
  335. + target = <&spi0>;
  336. + __dormant__ {
  337. + status = "okay";
  338. + #address-cells = <1>;
  339. + #size-cells = <0>;
  340. + mcp23s17_01: mcp23s17@1 {
  341. + compatible = "microchip,mcp23s17";
  342. + gpio-controller;
  343. + #gpio-cells = <2>;
  344. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi0-1-present parameter */
  345. + reg = <1>;
  346. + spi-max-frequency = <500000>;
  347. + status = "okay";
  348. + #interrupt-cells=<2>;
  349. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi0-1-int-gpio parameter */
  350. + };
  351. + };
  352. + };
  353. +
  354. + // enable one or more mcp23s17s on spi1.0
  355. + fragment@18 {
  356. + target = <&spi1>;
  357. + __dormant__ {
  358. + status = "okay";
  359. + #address-cells = <1>;
  360. + #size-cells = <0>;
  361. + mcp23s17_10: mcp23s17@0 {
  362. + compatible = "microchip,mcp23s17";
  363. + gpio-controller;
  364. + #gpio-cells = <2>;
  365. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi1-0-present parameter */
  366. + reg = <0>;
  367. + spi-max-frequency = <500000>;
  368. + status = "okay";
  369. + #interrupt-cells=<2>;
  370. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi1-0-int-gpio parameter */
  371. + };
  372. + };
  373. + };
  374. +
  375. + // enable one or more mcp23s17s on spi1.1
  376. + fragment@19 {
  377. + target = <&spi1>;
  378. + __dormant__ {
  379. + status = "okay";
  380. + #address-cells = <1>;
  381. + #size-cells = <0>;
  382. + mcp23s17_11: mcp23s17@1 {
  383. + compatible = "microchip,mcp23s17";
  384. + gpio-controller;
  385. + #gpio-cells = <2>;
  386. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi1-1-present parameter */
  387. + reg = <1>;
  388. + spi-max-frequency = <500000>;
  389. + status = "okay";
  390. + #interrupt-cells=<2>;
  391. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi1-1-int-gpio parameter */
  392. + };
  393. + };
  394. + };
  395. +
  396. + // enable one or more mcp23s17s on spi1.2
  397. + fragment@20 {
  398. + target = <&spi1>;
  399. + __dormant__ {
  400. + status = "okay";
  401. + #address-cells = <1>;
  402. + #size-cells = <0>;
  403. + mcp23s17_12: mcp23s17@2 {
  404. + compatible = "microchip,mcp23s17";
  405. + gpio-controller;
  406. + #gpio-cells = <2>;
  407. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi1-2-present parameter */
  408. + reg = <2>;
  409. + spi-max-frequency = <500000>;
  410. + status = "okay";
  411. + #interrupt-cells=<2>;
  412. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi1-2-int-gpio parameter */
  413. + };
  414. + };
  415. + };
  416. +
  417. + // enable one or more mcp23s17s on spi2.0
  418. + fragment@21 {
  419. + target = <&spi2>;
  420. + __dormant__ {
  421. + status = "okay";
  422. + #address-cells = <1>;
  423. + #size-cells = <0>;
  424. + mcp23s17_20: mcp23s17@0 {
  425. + compatible = "microchip,mcp23s17";
  426. + gpio-controller;
  427. + #gpio-cells = <2>;
  428. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi2-0-present parameter */
  429. + reg = <0>;
  430. + spi-max-frequency = <500000>;
  431. + status = "okay";
  432. + #interrupt-cells=<2>;
  433. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi2-0-int-gpio parameter */
  434. + };
  435. + };
  436. + };
  437. +
  438. + // enable one or more mcp23s17s on spi2.1
  439. + fragment@22 {
  440. + target = <&spi2>;
  441. + __dormant__ {
  442. + status = "okay";
  443. + #address-cells = <1>;
  444. + #size-cells = <0>;
  445. + mcp23s17_21: mcp23s17@1 {
  446. + compatible = "microchip,mcp23s17";
  447. + gpio-controller;
  448. + #gpio-cells = <2>;
  449. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi2-1-present parameter */
  450. + reg = <1>;
  451. + spi-max-frequency = <500000>;
  452. + status = "okay";
  453. + #interrupt-cells=<2>;
  454. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi2-1-int-gpio parameter */
  455. + };
  456. + };
  457. + };
  458. +
  459. + // enable one or more mcp23s17s on spi2.2
  460. + fragment@23 {
  461. + target = <&spi2>;
  462. + __dormant__ {
  463. + status = "okay";
  464. + #address-cells = <1>;
  465. + #size-cells = <0>;
  466. + mcp23s17_22: mcp23s17@2 {
  467. + compatible = "microchip,mcp23s17";
  468. + gpio-controller;
  469. + #gpio-cells = <2>;
  470. + microchip,spi-present-mask = <0x00>; /* overwritten by mcp23s17-spi2-2-present parameter */
  471. + reg = <2>;
  472. + spi-max-frequency = <500000>;
  473. + status = "okay";
  474. + #interrupt-cells=<2>;
  475. + interrupts = <0 2>; /* 1st word overwritten by mcp23s17-spi2-2-int-gpio parameter */
  476. + };
  477. + };
  478. + };
  479. +
  480. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.0 as a input with no pull-up/down
  481. + fragment@24 {
  482. + target = <&gpio>;
  483. + __dormant__ {
  484. + spi0_0_int_pins: spi0_0_int_pins {
  485. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi0-0-int-gpio parameter */
  486. + brcm,function = <0>;
  487. + brcm,pull = <0>;
  488. + };
  489. + };
  490. + };
  491. +
  492. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi0.1 as a input with no pull-up/down
  493. + fragment@25 {
  494. + target = <&gpio>;
  495. + __dormant__ {
  496. + spi0_1_int_pins: spi0_1_int_pins {
  497. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi0-1-int-gpio parameter */
  498. + brcm,function = <0>;
  499. + brcm,pull = <0>;
  500. + };
  501. + };
  502. + };
  503. +
  504. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.0 as a input with no pull-up/down
  505. + fragment@26 {
  506. + target = <&gpio>;
  507. + __dormant__ {
  508. + spi1_0_int_pins: spi1_0_int_pins {
  509. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi1-0-int-gpio parameter */
  510. + brcm,function = <0>;
  511. + brcm,pull = <0>;
  512. + };
  513. + };
  514. + };
  515. +
  516. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.1 as a input with no pull-up/down
  517. + fragment@27 {
  518. + target = <&gpio>;
  519. + __dormant__ {
  520. + spi1_1_int_pins: spi1_1_int_pins {
  521. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi1-1-int-gpio parameter */
  522. + brcm,function = <0>;
  523. + brcm,pull = <0>;
  524. + };
  525. + };
  526. + };
  527. +
  528. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi1.2 as a input with no pull-up/down
  529. + fragment@28 {
  530. + target = <&gpio>;
  531. + __dormant__ {
  532. + spi1_2_int_pins: spi1_2_int_pins {
  533. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi1-2-int-gpio parameter */
  534. + brcm,function = <0>;
  535. + brcm,pull = <0>;
  536. + };
  537. + };
  538. + };
  539. +
  540. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.0 as a input with no pull-up/down
  541. + fragment@29 {
  542. + target = <&gpio>;
  543. + __dormant__ {
  544. + spi2_0_int_pins: spi2_0_int_pins {
  545. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi2-0-int-gpio parameter */
  546. + brcm,function = <0>;
  547. + brcm,pull = <0>;
  548. + };
  549. + };
  550. + };
  551. +
  552. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.1 as a input with no pull-up/down
  553. + fragment@30 {
  554. + target = <&gpio>;
  555. + __dormant__ {
  556. + spi2_1_int_pins: spi2_1_int_pins {
  557. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi2-1-int-gpio parameter */
  558. + brcm,function = <0>;
  559. + brcm,pull = <0>;
  560. + };
  561. + };
  562. + };
  563. +
  564. + // Configure GPIO pin connected to INT(A/B) output of mcp23s08/17 on spi2.2 as a input with no pull-up/down
  565. + fragment@31 {
  566. + target = <&gpio>;
  567. + __dormant__ {
  568. + spi2_2_int_pins: spi2_2_int_pins {
  569. + brcm,pins = <0>; /* overwritten by mcp23s08/17-spi2-2-int-gpio parameter */
  570. + brcm,function = <0>;
  571. + brcm,pull = <0>;
  572. + };
  573. + };
  574. + };
  575. +
  576. + // Enable interrupts for a mcp23s08 on spi0.0.
  577. + // Use default active low interrupt signalling.
  578. + fragment@32 {
  579. + target = <&mcp23s08_00>;
  580. + __dormant__ {
  581. + interrupt-parent = <&gpio>;
  582. + interrupt-controller;
  583. + };
  584. + };
  585. +
  586. + // Enable interrupts for a mcp23s08 on spi0.1.
  587. + // Use default active low interrupt signalling.
  588. + fragment@33 {
  589. + target = <&mcp23s08_01>;
  590. + __dormant__ {
  591. + interrupt-parent = <&gpio>;
  592. + interrupt-controller;
  593. + };
  594. + };
  595. +
  596. + // Enable interrupts for a mcp23s08 on spi1.0.
  597. + // Use default active low interrupt signalling.
  598. + fragment@34 {
  599. + target = <&mcp23s08_10>;
  600. + __dormant__ {
  601. + interrupt-parent = <&gpio>;
  602. + interrupt-controller;
  603. + };
  604. + };
  605. +
  606. + // Enable interrupts for a mcp23s08 on spi1.1.
  607. + // Use default active low interrupt signalling.
  608. + fragment@35 {
  609. + target = <&mcp23s08_11>;
  610. + __dormant__ {
  611. + interrupt-parent = <&gpio>;
  612. + interrupt-controller;
  613. + };
  614. + };
  615. +
  616. + // Enable interrupts for a mcp23s08 on spi1.2.
  617. + // Use default active low interrupt signalling.
  618. + fragment@36 {
  619. + target = <&mcp23s08_12>;
  620. + __dormant__ {
  621. + interrupt-parent = <&gpio>;
  622. + interrupt-controller;
  623. + };
  624. + };
  625. +
  626. + // Enable interrupts for a mcp23s08 on spi2.0.
  627. + // Use default active low interrupt signalling.
  628. + fragment@37 {
  629. + target = <&mcp23s08_20>;
  630. + __dormant__ {
  631. + interrupt-parent = <&gpio>;
  632. + interrupt-controller;
  633. + };
  634. + };
  635. +
  636. + // Enable interrupts for a mcp23s08 on spi2.1.
  637. + // Use default active low interrupt signalling.
  638. + fragment@38 {
  639. + target = <&mcp23s08_21>;
  640. + __dormant__ {
  641. + interrupt-parent = <&gpio>;
  642. + interrupt-controller;
  643. + };
  644. + };
  645. +
  646. + // Enable interrupts for a mcp23s08 on spi2.2.
  647. + // Use default active low interrupt signalling.
  648. + fragment@39 {
  649. + target = <&mcp23s08_22>;
  650. + __dormant__ {
  651. + interrupt-parent = <&gpio>;
  652. + interrupt-controller;
  653. + };
  654. + };
  655. +
  656. + // Enable interrupts for a mcp23s17 on spi0.0.
  657. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  658. + // Use default active low interrupt signalling.
  659. + fragment@40 {
  660. + target = <&mcp23s17_00>;
  661. + __dormant__ {
  662. + interrupt-parent = <&gpio>;
  663. + interrupt-controller;
  664. + microchip,irq-mirror;
  665. + };
  666. + };
  667. +
  668. + // Enable interrupts for a mcp23s17 on spi0.1.
  669. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  670. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  671. + fragment@41 {
  672. + target = <&mcp23s17_01>;
  673. + __dormant__ {
  674. + interrupt-parent = <&gpio>;
  675. + interrupt-controller;
  676. + microchip,irq-mirror;
  677. + };
  678. + };
  679. +
  680. + // Enable interrupts for a mcp23s17 on spi1.0.
  681. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  682. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  683. + fragment@42 {
  684. + target = <&mcp23s17_10>;
  685. + __dormant__ {
  686. + interrupt-parent = <&gpio>;
  687. + interrupt-controller;
  688. + microchip,irq-mirror;
  689. + };
  690. + };
  691. +
  692. + // Enable interrupts for a mcp23s17 on spi1.1.
  693. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  694. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  695. + fragment@43 {
  696. + target = <&mcp23s17_11>;
  697. + __dormant__ {
  698. + interrupt-parent = <&gpio>;
  699. + interrupt-controller;
  700. + microchip,irq-mirror;
  701. + };
  702. + };
  703. +
  704. + // Enable interrupts for a mcp23s17 on spi1.2.
  705. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  706. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  707. + fragment@44 {
  708. + target = <&mcp23s17_12>;
  709. + __dormant__ {
  710. + interrupt-parent = <&gpio>;
  711. + interrupt-controller;
  712. + microchip,irq-mirror;
  713. + };
  714. + };
  715. +
  716. + // Enable interrupts for a mcp23s17 on spi2.0.
  717. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  718. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  719. + fragment@45 {
  720. + target = <&mcp23s17_20>;
  721. + __dormant__ {
  722. + interrupt-parent = <&gpio>;
  723. + interrupt-controller;
  724. + microchip,irq-mirror;
  725. + };
  726. + };
  727. +
  728. + // Enable interrupts for a mcp23s17 on spi2.1.
  729. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  730. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  731. + fragment@46 {
  732. + target = <&mcp23s17_21>;
  733. + __dormant__ {
  734. + interrupt-parent = <&gpio>;
  735. + interrupt-controller;
  736. + microchip,irq-mirror;
  737. + };
  738. + };
  739. +
  740. + // Enable interrupts for a mcp23s17 on spi2.2.
  741. + // Enable mirroring so that either INTA or INTB output of mcp23s17 can be connected to the GPIO pin.
  742. + // Configure INTA/B outputs of mcp23s08/17 as active low.
  743. + fragment@47 {
  744. + target = <&mcp23s17_22>;
  745. + __dormant__ {
  746. + interrupt-parent = <&gpio>;
  747. + interrupt-controller;
  748. + microchip,irq-mirror;
  749. + };
  750. + };
  751. +
  752. + __overrides__ {
  753. + s08-spi0-0-present = <0>,"+0+8", <&mcp23s08_00>,"microchip,spi-present-mask:0";
  754. + s08-spi0-1-present = <0>,"+1+9", <&mcp23s08_01>,"microchip,spi-present-mask:0";
  755. + s08-spi1-0-present = <0>,"+2+10", <&mcp23s08_10>,"microchip,spi-present-mask:0";
  756. + s08-spi1-1-present = <0>,"+3+11", <&mcp23s08_11>,"microchip,spi-present-mask:0";
  757. + s08-spi1-2-present = <0>,"+4+12", <&mcp23s08_12>,"microchip,spi-present-mask:0";
  758. + s08-spi2-0-present = <0>,"+5+13", <&mcp23s08_20>,"microchip,spi-present-mask:0";
  759. + s08-spi2-1-present = <0>,"+6+14", <&mcp23s08_21>,"microchip,spi-present-mask:0";
  760. + s08-spi2-2-present = <0>,"+7+15", <&mcp23s08_22>,"microchip,spi-present-mask:0";
  761. + s17-spi0-0-present = <0>,"+0+16", <&mcp23s17_00>,"microchip,spi-present-mask:0";
  762. + s17-spi0-1-present = <0>,"+1+17", <&mcp23s17_01>,"microchip,spi-present-mask:0";
  763. + s17-spi1-0-present = <0>,"+2+18", <&mcp23s17_10>,"microchip,spi-present-mask:0";
  764. + s17-spi1-1-present = <0>,"+3+19", <&mcp23s17_11>,"microchip,spi-present-mask:0";
  765. + s17-spi1-2-present = <0>,"+4+20", <&mcp23s17_12>,"microchip,spi-present-mask:0";
  766. + s17-spi2-0-present = <0>,"+5+21", <&mcp23s17_20>,"microchip,spi-present-mask:0";
  767. + s17-spi2-1-present = <0>,"+6+22", <&mcp23s17_21>,"microchip,spi-present-mask:0";
  768. + s17-spi2-2-present = <0>,"+7+23", <&mcp23s17_22>,"microchip,spi-present-mask:0";
  769. + s08-spi0-0-int-gpio = <0>,"+24+32", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s08_00>,"interrupts:0";
  770. + s08-spi0-1-int-gpio = <0>,"+25+33", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s08_01>,"interrupts:0";
  771. + s08-spi1-0-int-gpio = <0>,"+26+34", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s08_10>,"interrupts:0";
  772. + s08-spi1-1-int-gpio = <0>,"+27+35", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s08_11>,"interrupts:0";
  773. + s08-spi1-2-int-gpio = <0>,"+28+36", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s08_12>,"interrupts:0";
  774. + s08-spi2-0-int-gpio = <0>,"+29+37", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s08_20>,"interrupts:0";
  775. + s08-spi2-1-int-gpio = <0>,"+30+38", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s08_21>,"interrupts:0";
  776. + s08-spi2-2-int-gpio = <0>,"+31+39", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s08_22>,"interrupts:0";
  777. + s17-spi0-0-int-gpio = <0>,"+24+40", <&spi0_0_int_pins>,"brcm,pins:0", <&mcp23s17_00>,"interrupts:0";
  778. + s17-spi0-1-int-gpio = <0>,"+25+41", <&spi0_1_int_pins>,"brcm,pins:0", <&mcp23s17_01>,"interrupts:0";
  779. + s17-spi1-0-int-gpio = <0>,"+26+42", <&spi1_0_int_pins>,"brcm,pins:0", <&mcp23s17_10>,"interrupts:0";
  780. + s17-spi1-1-int-gpio = <0>,"+27+43", <&spi1_1_int_pins>,"brcm,pins:0", <&mcp23s17_11>,"interrupts:0";
  781. + s17-spi1-2-int-gpio = <0>,"+28+44", <&spi1_2_int_pins>,"brcm,pins:0", <&mcp23s17_12>,"interrupts:0";
  782. + s17-spi2-0-int-gpio = <0>,"+29+45", <&spi2_0_int_pins>,"brcm,pins:0", <&mcp23s17_20>,"interrupts:0";
  783. + s17-spi2-1-int-gpio = <0>,"+30+46", <&spi2_1_int_pins>,"brcm,pins:0", <&mcp23s17_21>,"interrupts:0";
  784. + s17-spi2-2-int-gpio = <0>,"+31+47", <&spi2_2_int_pins>,"brcm,pins:0", <&mcp23s17_22>,"interrupts:0";
  785. + };
  786. +};
  787. +