| 12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273 |
- From 471248ef11464161346bd623becb383625122162 Mon Sep 17 00:00:00 2001
- From: Martin Sperl <kernel@martin.sperl.org>
- Date: Mon, 29 Feb 2016 15:43:56 +0000
- Subject: [PATCH] clk: bcm2835: add missing PLL clock dividers
- Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
- Signed-off-by: Eric Anholt <eric@anholt.net>
- Reviewed-by: Eric Anholt <eric@anholt.net>
- (cherry picked from commit 728436956aa172b24a3212295f8b53feb6479f32)
- ---
- drivers/clk/bcm/clk-bcm2835.c | 32 ++++++++++++++++++++++++++++++++
- include/dt-bindings/clock/bcm2835.h | 5 +++++
- 2 files changed, 37 insertions(+)
- --- a/drivers/clk/bcm/clk-bcm2835.c
- +++ b/drivers/clk/bcm/clk-bcm2835.c
- @@ -1395,6 +1395,22 @@ static const struct bcm2835_clk_desc clk
- .load_mask = CM_PLLA_LOADPER,
- .hold_mask = CM_PLLA_HOLDPER,
- .fixed_divider = 1),
- + [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
- + .name = "plla_dsi0",
- + .source_pll = "plla",
- + .cm_reg = CM_PLLA,
- + .a2w_reg = A2W_PLLA_DSI0,
- + .load_mask = CM_PLLA_LOADDSI0,
- + .hold_mask = CM_PLLA_HOLDDSI0,
- + .fixed_divider = 1),
- + [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
- + .name = "plla_ccp2",
- + .source_pll = "plla",
- + .cm_reg = CM_PLLA,
- + .a2w_reg = A2W_PLLA_CCP2,
- + .load_mask = CM_PLLA_LOADCCP2,
- + .hold_mask = CM_PLLA_HOLDCCP2,
- + .fixed_divider = 1),
-
- /* PLLB is used for the ARM's clock. */
- [BCM2835_PLLB] = REGISTER_PLL(
- @@ -1509,6 +1525,22 @@ static const struct bcm2835_clk_desc clk
- .load_mask = CM_PLLD_LOADPER,
- .hold_mask = CM_PLLD_HOLDPER,
- .fixed_divider = 1),
- + [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
- + .name = "plld_dsi0",
- + .source_pll = "plld",
- + .cm_reg = CM_PLLD,
- + .a2w_reg = A2W_PLLD_DSI0,
- + .load_mask = CM_PLLD_LOADDSI0,
- + .hold_mask = CM_PLLD_HOLDDSI0,
- + .fixed_divider = 1),
- + [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
- + .name = "plld_dsi1",
- + .source_pll = "plld",
- + .cm_reg = CM_PLLD,
- + .a2w_reg = A2W_PLLD_DSI1,
- + .load_mask = CM_PLLD_LOADDSI1,
- + .hold_mask = CM_PLLD_HOLDDSI1,
- + .fixed_divider = 1),
-
- /*
- * PLLH is used to supply the pixel clock or the AUX clock for the
- --- a/include/dt-bindings/clock/bcm2835.h
- +++ b/include/dt-bindings/clock/bcm2835.h
- @@ -45,3 +45,8 @@
- #define BCM2835_CLOCK_PERI_IMAGE 29
- #define BCM2835_CLOCK_PWM 30
- #define BCM2835_CLOCK_PCM 31
- +
- +#define BCM2835_PLLA_DSI0 32
- +#define BCM2835_PLLA_CCP2 33
- +#define BCM2835_PLLD_DSI0 34
- +#define BCM2835_PLLD_DSI1 35
|
