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apm821xx
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patches-4.4
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300-fix-atheros-nics-on-apm82181.patch

300-fix-atheros-nics-on-apm82181.patch 1.8 KB
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  1. --- a/arch/powerpc/sysdev/ppc4xx_pci.c
    2. 

  2. +++ b/arch/powerpc/sysdev/ppc4xx_pci.c
    3. 

  3. @@ -1066,15 +1066,24 @@ static int __init apm821xx_pciex_init_po
    4. 

  4.  	u32 val;
    5. 

  5.  
    6. 

  6.  	/*
    7. 

  7. -	 * Do a software reset on PCIe ports.
    8. 

  8. -	 * This code is to fix the issue that pci drivers doesn't re-assign
    9. 

  9. -	 * bus number for PCIE devices after Uboot
    10. 

  10. -	 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
    11. 

  11. -	 * PT quad port, SAS LSI 1064E)
    12. 

  12. +	 * Only reset the PHY when no link is currently established.
    13. 

  13. +	 * This is for the Atheros PCIe board which has problems to establish
    14. 

  14. +	 * the link (again) after this PHY reset. All other currently tested
    15. 

  15. +	 * PCIe boards don't show this problem.
    16. 

  16.  	 */
    17. 

  17. -
    18. 

  18. -	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
    19. 

  19. -	mdelay(10);
    20. 

  20. +	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
    21. 

  21. +	if (!(val & 0x00001000)) {
    22. 

  22. +		/*
    23. 

  23. +		 * Do a software reset on PCIe ports.
    24. 

  24. +		 * This code is to fix the issue that pci drivers doesn't re-assign
    25. 

  25. +		 * bus number for PCIE devices after Uboot
    26. 

  26. +		 * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
    27. 

  27. +		 * PT quad port, SAS LSI 1064E)
    28. 

  28. +		 */
    29. 

  29. +
    30. 

  30. +		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
    31. 

  31. +		mdelay(10);
    32. 

  32. +	}
    33. 

  33.  
    34. 

  34.  	if (port->endpoint)
    35. 

  35.  		val = PTYPE_LEGACY_ENDPOINT << 20;
    36. 

  36. @@ -1091,9 +1100,12 @@ static int __init apm821xx_pciex_init_po
    37. 

  37.  	mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
    38. 

  38.  	mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
    39. 

  39.  
    40. 

  40. -	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
    41. 

  41. -	mdelay(50);
    42. 

  42. -	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
    43. 

  43. +	val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
    44. 

  44. +	if (!(val & 0x00001000)) {
    45. 

  45. +		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
    46. 

  46. +		mdelay(50);
    47. 

  47. +		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
    48. 

  48. +	}
    49. 

  49.  
    50. 

  50.  	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
    51. 

  51.  		mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
    52.