From 6ef5cf7b8f6b86fb3856f3449f1ad431118e5c9d Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Wed, 22 Apr 2015 13:07:25 -0400 Subject: [PATCH 33/70] arm64: add ioremap for normal cacheable non-shareable memory [context adjustment] Signed-off-by: Haiying Wang Change-Id: Iab7413f182a64bd6ad4707dd1d6254d04f51a3b1 Reviewed-on: http://git.am.freescale.net:8181/35486 Tested-by: Review Code-CDREVIEW Reviewed-by: Roy Pledge Reviewed-by: Stuart Yoder Integrated-by: Jiang Yutang --- arch/arm64/include/asm/io.h | 2 ++ arch/arm64/include/asm/pgtable.h | 2 ++ 2 files changed, 4 insertions(+) --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -171,6 +171,8 @@ extern void __iomem *ioremap_cache(phys_ #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) +#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), \ + __pgprot(PROT_NORMAL_NS)) #define iounmap __iounmap /* --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -74,6 +74,8 @@ extern void __pgd_error(const char *file #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC)) #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT)) #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) +#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | \ + PTE_ATTRINDX(MT_NORMAL)) #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))