0052-i2c-MIPS-adds-ralink-I2C-driver.patch 9.2 KB

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  1. From 225f36695bb07dad9510f9affd79e63f1a44a195 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 09:52:56 +0100
  4. Subject: [PATCH 52/57] i2c: MIPS: adds ralink I2C driver
  5. Signed-off-by: John Crispin <blogic@openwrt.org>
  6. ---
  7. .../devicetree/bindings/i2c/i2c-ralink.txt | 27 ++
  8. drivers/i2c/busses/Kconfig | 4 +
  9. drivers/i2c/busses/Makefile | 1 +
  10. drivers/i2c/busses/i2c-ralink.c | 274 ++++++++++++++++++++
  11. 4 files changed, 306 insertions(+)
  12. create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  13. create mode 100644 drivers/i2c/busses/i2c-ralink.c
  14. --- /dev/null
  15. +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  16. @@ -0,0 +1,27 @@
  17. +I2C for Ralink platforms
  18. +
  19. +Required properties :
  20. +- compatible : Must be "link,rt3052-i2c"
  21. +- reg: physical base address of the controller and length of memory mapped
  22. + region.
  23. +- #address-cells = <1>;
  24. +- #size-cells = <0>;
  25. +
  26. +Optional properties:
  27. +- Child nodes conforming to i2c bus binding
  28. +
  29. +Example :
  30. +
  31. +palmbus@10000000 {
  32. + i2c@900 {
  33. + compatible = "link,rt3052-i2c";
  34. + reg = <0x900 0x100>;
  35. + #address-cells = <1>;
  36. + #size-cells = <0>;
  37. +
  38. + hwmon@4b {
  39. + compatible = "national,lm92";
  40. + reg = <0x4b>;
  41. + };
  42. + };
  43. +};
  44. --- a/drivers/i2c/busses/Kconfig
  45. +++ b/drivers/i2c/busses/Kconfig
  46. @@ -711,6 +711,10 @@ config I2C_RK3X
  47. This driver can also be built as a module. If so, the module will
  48. be called i2c-rk3x.
  49. +config I2C_RALINK
  50. + tristate "Ralink I2C Controller"
  51. + select OF_I2C
  52. +
  53. config HAVE_S3C2410_I2C
  54. bool
  55. help
  56. --- a/drivers/i2c/busses/Makefile
  57. +++ b/drivers/i2c/busses/Makefile
  58. @@ -66,6 +66,7 @@ obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
  59. obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
  60. obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
  61. obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
  62. +obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
  63. obj-$(CONFIG_I2C_QUP) += i2c-qup.o
  64. obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
  65. obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
  66. --- /dev/null
  67. +++ b/drivers/i2c/busses/i2c-ralink.c
  68. @@ -0,0 +1,308 @@
  69. +/*
  70. + * drivers/i2c/busses/i2c-ralink.c
  71. + *
  72. + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  73. + *
  74. + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  75. + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  76. + *
  77. + * This software is licensed under the terms of the GNU General Public
  78. + * License version 2, as published by the Free Software Foundation, and
  79. + * may be copied, distributed, and modified under those terms.
  80. + *
  81. + * This program is distributed in the hope that it will be useful,
  82. + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  83. + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  84. + * GNU General Public License for more details.
  85. + *
  86. + */
  87. +
  88. +#include <linux/interrupt.h>
  89. +#include <linux/kernel.h>
  90. +#include <linux/module.h>
  91. +#include <linux/reset.h>
  92. +#include <linux/delay.h>
  93. +#include <linux/slab.h>
  94. +#include <linux/init.h>
  95. +#include <linux/errno.h>
  96. +#include <linux/platform_device.h>
  97. +#include <linux/of_platform.h>
  98. +#include <linux/i2c.h>
  99. +#include <linux/io.h>
  100. +#include <linux/err.h>
  101. +
  102. +#include <asm/mach-ralink/ralink_regs.h>
  103. +
  104. +#define REG_CONFIG_REG 0x00
  105. +#define REG_CLKDIV_REG 0x04
  106. +#define REG_DEVADDR_REG 0x08
  107. +#define REG_ADDR_REG 0x0C
  108. +#define REG_DATAOUT_REG 0x10
  109. +#define REG_DATAIN_REG 0x14
  110. +#define REG_STATUS_REG 0x18
  111. +#define REG_STARTXFR_REG 0x1C
  112. +#define REG_BYTECNT_REG 0x20
  113. +#define REG_SM0CFG2 0x28
  114. +#define REG_SM0CTL0 0x40
  115. +
  116. +#define SYSC_REG_RESET_CTRL 0x34
  117. +
  118. +#define I2C_RST (1<<16)
  119. +#define I2C_STARTERR BIT(4)
  120. +#define I2C_ACKERR BIT(3)
  121. +#define I2C_DATARDY BIT(2)
  122. +#define I2C_SDOEMPTY BIT(1)
  123. +#define I2C_BUSY BIT(0)
  124. +
  125. +#define I2C_DEVADLEN_7 (6 << 2)
  126. +#define I2C_ADDRDIS BIT(1)
  127. +
  128. +#define CLKDIV_VALUE 200
  129. +
  130. +#define READ_CMD 0x01
  131. +#define WRITE_CMD 0x00
  132. +#define READ_BLOCK 64
  133. +
  134. +#define SM0CTL0_OD BIT(31)
  135. +#define SM0CTL0_VTRIG BIT(28)
  136. +#define SM0CTL0_OUTHI BIT(6)
  137. +#define SM0CTL0_STRETCH BIT(1)
  138. +#define SM0CTL0_DEFAULT (SM0CTL0_OD | SM0CTL0_VTRIG | SM0CTL0_OUTHI | SM0CTL0_STRETCH)
  139. +
  140. +#define MAX_SIZE 63
  141. +
  142. +enum {
  143. + I2C_TYPE_RALINK,
  144. + I2C_TYPE_MEDIATEK,
  145. +};
  146. +
  147. +static void __iomem *membase;
  148. +static struct i2c_adapter *adapter;
  149. +static int hw_type;
  150. +
  151. +static void rt_i2c_w32(u32 val, unsigned reg)
  152. +{
  153. + iowrite32(val, membase + reg);
  154. +}
  155. +
  156. +static u32 rt_i2c_r32(unsigned reg)
  157. +{
  158. + return ioread32(membase + reg);
  159. +}
  160. +
  161. +static void rt_i2c_default_speed(void)
  162. +{
  163. + if (hw_type == I2C_TYPE_RALINK) {
  164. + rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
  165. + } else {
  166. + rt_i2c_w32((CLKDIV_VALUE << 16) | SM0CTL0_DEFAULT, REG_SM0CTL0);
  167. + rt_i2c_w32(1, REG_SM0CFG2);
  168. + }
  169. +}
  170. +
  171. +static void rt_i2c_init(struct i2c_adapter *a)
  172. +{/*
  173. + u32 val;
  174. +
  175. + val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
  176. + val |= I2C_RST;
  177. + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
  178. +
  179. + val &= ~I2C_RST;
  180. + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
  181. +*/
  182. + device_reset(a->dev.parent);
  183. +
  184. + udelay(500);
  185. + rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
  186. +
  187. + rt_i2c_default_speed();
  188. +}
  189. +
  190. +static inline int rt_i2c_wait_rx_done(void)
  191. +{
  192. + while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
  193. + return 0;
  194. +}
  195. +
  196. +static inline int rt_i2c_wait_idle(void)
  197. +{
  198. + while (rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
  199. + return 0;
  200. +}
  201. +
  202. +static inline int rt_i2c_wait_tx_done(void)
  203. +{
  204. + while (!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
  205. + return 0;
  206. +}
  207. +
  208. +static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
  209. +{
  210. + int i = 0, j = 0, pos = 0;
  211. + int nblock = msg->len / READ_BLOCK;
  212. + int rem = msg->len % READ_BLOCK;
  213. + int ret = 0;
  214. +
  215. + if (msg->flags & I2C_M_TEN) {
  216. + printk("10 bits addr not supported\n");
  217. + return -EINVAL;
  218. + }
  219. +
  220. + if (msg->len > MAX_SIZE) {
  221. + printk("Notice! The FIFO data length is 64 Byte\n");
  222. + return -EINVAL;
  223. + }
  224. +
  225. + if (msg->flags & I2C_M_RD) {
  226. + for (i = 0; i < nblock; i++) {
  227. + rt_i2c_wait_idle();
  228. + rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
  229. + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
  230. + for (j = 0; j < READ_BLOCK; j++) {
  231. + rt_i2c_wait_rx_done();
  232. + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
  233. + }
  234. + }
  235. +
  236. + rt_i2c_wait_idle();
  237. + if (rem) {
  238. + rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
  239. + rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
  240. + }
  241. + for (i = 0; i < rem; i++) {
  242. + rt_i2c_wait_rx_done();
  243. + msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
  244. + }
  245. + } else {
  246. + rt_i2c_wait_idle();
  247. + rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
  248. + for (i = 0; i < msg->len; i++) {
  249. + rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
  250. + if (i == 0)
  251. + rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
  252. + rt_i2c_wait_tx_done();
  253. + }
  254. + //mdelay(2);
  255. + }
  256. +
  257. + return ret;
  258. +}
  259. +
  260. +static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
  261. +{
  262. + int i = 0;
  263. + int ret = 0;
  264. +
  265. + rt_i2c_w32(m->addr, REG_DEVADDR_REG);
  266. + rt_i2c_w32(0, REG_ADDR_REG);
  267. +
  268. + for (i = 0; ret == 0 && i !=n; i++) {
  269. + ret = rt_i2c_handle_msg(a, &m[i]);
  270. +
  271. + if (ret < 0) {
  272. + return ret;
  273. + }
  274. + }
  275. +
  276. + return i;
  277. +}
  278. +
  279. +static u32 rt_i2c_func(struct i2c_adapter *a)
  280. +{
  281. + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  282. +}
  283. +
  284. +static const struct i2c_algorithm rt_i2c_algo = {
  285. + .master_xfer = rt_i2c_master_xfer,
  286. + .functionality = rt_i2c_func,
  287. +};
  288. +
  289. +static const struct of_device_id i2c_rt_dt_ids[] = {
  290. + { .compatible = "ralink,rt2880-i2c", .data = (void *) I2C_TYPE_RALINK },
  291. + { .compatible = "mediatek,mt7628-i2c", .data = (void *) I2C_TYPE_MEDIATEK },
  292. + { /* sentinel */ }
  293. +};
  294. +
  295. +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
  296. +
  297. +static int rt_i2c_probe(struct platform_device *pdev)
  298. +{
  299. + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  300. + const struct of_device_id *match;
  301. + int ret;
  302. +
  303. + match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
  304. + hw_type = (int) match->data;
  305. +
  306. + if (!res) {
  307. + dev_err(&pdev->dev, "no memory resource found\n");
  308. + return -ENODEV;
  309. + }
  310. +
  311. + adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
  312. + if (!adapter) {
  313. + dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
  314. + return -ENOMEM;
  315. + }
  316. +
  317. + membase = devm_ioremap_resource(&pdev->dev, res);
  318. + if (IS_ERR(membase))
  319. + return PTR_ERR(membase);
  320. +
  321. + strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
  322. + adapter->owner = THIS_MODULE;
  323. + adapter->nr = pdev->id;
  324. + adapter->timeout = HZ;
  325. + adapter->algo = &rt_i2c_algo;
  326. + adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  327. + adapter->dev.parent = &pdev->dev;
  328. + adapter->dev.of_node = pdev->dev.of_node;
  329. +
  330. + ret = i2c_add_numbered_adapter(adapter);
  331. + if (ret)
  332. + return ret;
  333. +
  334. + platform_set_drvdata(pdev, adapter);
  335. +
  336. + rt_i2c_init(adapter);
  337. +
  338. + dev_info(&pdev->dev, "loaded\n");
  339. +
  340. + return 0;
  341. +}
  342. +
  343. +static int rt_i2c_remove(struct platform_device *pdev)
  344. +{
  345. + platform_set_drvdata(pdev, NULL);
  346. +
  347. + return 0;
  348. +}
  349. +
  350. +static struct platform_driver rt_i2c_driver = {
  351. + .probe = rt_i2c_probe,
  352. + .remove = rt_i2c_remove,
  353. + .driver = {
  354. + .owner = THIS_MODULE,
  355. + .name = "i2c-ralink",
  356. + .of_match_table = i2c_rt_dt_ids,
  357. + },
  358. +};
  359. +
  360. +static int __init i2c_rt_init (void)
  361. +{
  362. + return platform_driver_register(&rt_i2c_driver);
  363. +}
  364. +subsys_initcall(i2c_rt_init);
  365. +
  366. +static void __exit i2c_rt_exit (void)
  367. +{
  368. + platform_driver_unregister(&rt_i2c_driver);
  369. +}
  370. +
  371. +module_exit (i2c_rt_exit);
  372. +
  373. +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
  374. +MODULE_DESCRIPTION("Ralink I2c host driver");
  375. +MODULE_LICENSE("GPL");
  376. +MODULE_ALIAS("platform:Ralink-I2C");