095-gpio_support.patch 2.1 KB

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  1. --- a/arch/arm/mach-cns3xxx/cns3420vb.c
  2. +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
  3. @@ -245,6 +245,10 @@ static void __init cns3420_init(void)
  4. cns3xxx_ahci_init();
  5. cns3xxx_sdhci_init();
  6. + cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
  7. + NR_IRQS_CNS3XXX);
  8. + cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
  9. + NR_IRQS_CNS3XXX + 32);
  10. pm_power_off = cns3xxx_power_off;
  11. }
  12. --- a/arch/arm/mach-cns3xxx/Kconfig
  13. +++ b/arch/arm/mach-cns3xxx/Kconfig
  14. @@ -1,6 +1,8 @@
  15. menuconfig ARCH_CNS3XXX
  16. bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
  17. select ARM_GIC
  18. + select ARCH_REQUIRE_GPIOLIB
  19. + select GENERIC_IRQ_CHIP
  20. select PCI_DOMAINS if PCI
  21. select HAVE_ARM_SCU if SMP
  22. select HAVE_ARM_TWD if LOCAL_TIMERS
  23. --- a/arch/arm/mach-cns3xxx/Makefile
  24. +++ b/arch/arm/mach-cns3xxx/Makefile
  25. @@ -1,7 +1,7 @@
  26. ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
  27. obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o
  28. -cns3xxx-y += core.o pm.o
  29. +cns3xxx-y += core.o pm.o gpio.o
  30. cns3xxx-$(CONFIG_ATAGS) += devices.o
  31. cns3xxx-$(CONFIG_PCI) += pcie.o
  32. CFLAGS_pcie.o += -Wframe-larger-than=1536 # override default 1024, this is safe here
  33. --- a/arch/arm/mach-cns3xxx/cns3xxx.h
  34. +++ b/arch/arm/mach-cns3xxx/cns3xxx.h
  35. @@ -68,8 +68,10 @@
  36. #define SMC_PCELL_ID_3_OFFSET 0xFFC
  37. #define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
  38. +#define CNS3XXX_GPIOA_BASE_VIRT 0xFB006000
  39. #define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
  40. +#define CNS3XXX_GPIOB_BASE_VIRT 0xFB007000
  41. #define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
  42. --- a/arch/arm/mach-cns3xxx/core.c
  43. +++ b/arch/arm/mach-cns3xxx/core.c
  44. @@ -50,6 +50,16 @@ static struct map_desc cns3xxx_io_desc[]
  45. .pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
  46. .length = SZ_4K,
  47. .type = MT_DEVICE,
  48. + }, {
  49. + .virtual = CNS3XXX_GPIOA_BASE_VIRT,
  50. + .pfn = __phys_to_pfn(CNS3XXX_GPIOA_BASE),
  51. + .length = SZ_4K,
  52. + .type = MT_DEVICE,
  53. + }, {
  54. + .virtual = CNS3XXX_GPIOB_BASE_VIRT,
  55. + .pfn = __phys_to_pfn(CNS3XXX_GPIOB_BASE),
  56. + .length = SZ_4K,
  57. + .type = MT_DEVICE,
  58. #ifdef CONFIG_PCI
  59. }, {
  60. .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,