330-MIPS-BCM63XX-add-a-new-cpu-variant-helper.patch 2.5 KB

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  1. From c50acd37b425a8a907a6f7f93aa2e658256e79ce Mon Sep 17 00:00:00 2001
  2. From: Jonas Gorski <jogo@openwrt.org>
  3. Date: Sat, 7 Dec 2013 14:08:36 +0100
  4. Subject: [PATCH 40/53] MIPS: BCM63XX: add a new cpu variant helper
  5. ---
  6. arch/mips/bcm63xx/cpu.c | 10 ++++++++++
  7. arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++++++++++++
  8. 2 files changed, 28 insertions(+)
  9. --- a/arch/mips/bcm63xx/cpu.c
  10. +++ b/arch/mips/bcm63xx/cpu.c
  11. @@ -27,6 +27,8 @@ EXPORT_SYMBOL(bcm63xx_irqs);
  12. u16 bcm63xx_cpu_id __read_mostly;
  13. EXPORT_SYMBOL(bcm63xx_cpu_id);
  14. +static u32 bcm63xx_cpu_variant __read_mostly;
  15. +
  16. static u8 bcm63xx_cpu_rev;
  17. static unsigned int bcm63xx_cpu_freq;
  18. static unsigned int bcm63xx_memory_size;
  19. @@ -99,6 +101,13 @@ static const int bcm6368_irqs[] = {
  20. };
  21. +u32 bcm63xx_get_cpu_variant(void)
  22. +{
  23. + return bcm63xx_cpu_variant;
  24. +}
  25. +
  26. +EXPORT_SYMBOL(bcm63xx_get_cpu_variant);
  27. +
  28. u8 bcm63xx_get_cpu_rev(void)
  29. {
  30. return bcm63xx_cpu_rev;
  31. @@ -333,6 +342,7 @@ void __init bcm63xx_cpu_init(void)
  32. /* read out CPU type */
  33. tmp = bcm_readl(chipid_reg);
  34. bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
  35. + bcm63xx_cpu_variant = bcm63xx_cpu_id;
  36. bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
  37. switch (bcm63xx_cpu_id) {
  38. --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  39. +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  40. @@ -19,6 +19,7 @@
  41. #define BCM6368_CPU_ID 0x6368
  42. void __init bcm63xx_cpu_init(void);
  43. +u32 bcm63xx_get_cpu_variant(void);
  44. u8 bcm63xx_get_cpu_rev(void);
  45. unsigned int bcm63xx_get_cpu_freq(void);
  46. @@ -82,6 +83,23 @@ static inline u16 __pure bcm63xx_get_cpu
  47. #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
  48. #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
  49. +#define BCMCPU_VARIANT_IS_3368() \
  50. + (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
  51. +#define BCMCPU_VARIANT_IS_6328() \
  52. + (bcm63xx_get_cpu_variant() == BCM6328_CPU_ID)
  53. +#define BCMCPU_VARIANT_IS_6338() \
  54. + (bcm63xx_get_cpu_variant() == BCM6338_CPU_ID)
  55. +#define BCMCPU_VARIANT_IS_6345() \
  56. + (bcm63xx_get_cpu_variant() == BCM6345_CPU_ID)
  57. +#define BCMCPU_VARIANT_IS_6348() \
  58. + (bcm63xx_get_cpu_variant() == BCM6348_CPU_ID)
  59. +#define BCMCPU_VARIANT_IS_6358() \
  60. + (bcm63xx_get_cpu_cariant() == BCM6358_CPU_ID)
  61. +#define BCMCPU_VARIANT_IS_6362() \
  62. + (bcm63xx_get_cpu_variant() == BCM6362_CPU_ID)
  63. +#define BCMCPU_VARIANT_IS_6368() \
  64. + (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
  65. +
  66. /*
  67. * While registers sets are (mostly) the same across 63xx CPU, base
  68. * address of these sets do change.