0001-MIPS-ralink-add-verbose-pmu-info.patch 1.5 KB

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  1. From 453850d315070678245f61202ae343153589e5a6 Mon Sep 17 00:00:00 2001
  2. From: John Crispin <blogic@openwrt.org>
  3. Date: Sun, 27 Jul 2014 09:16:50 +0100
  4. Subject: [PATCH 01/57] MIPS: ralink: add verbose pmu info
  5. Print the PMU and LDO settings on boot.
  6. Signed-off-by: John Crispin <blogic@openwrt.org>
  7. ---
  8. arch/mips/ralink/mt7620.c | 26 ++++++++++++++++++++++++++
  9. 1 file changed, 26 insertions(+)
  10. --- a/arch/mips/ralink/mt7620.c
  11. +++ b/arch/mips/ralink/mt7620.c
  12. @@ -20,6 +20,22 @@
  13. #include "common.h"
  14. +/* analog */
  15. +#define PMU0_CFG 0x88
  16. +#define PMU_SW_SET BIT(28)
  17. +#define A_DCDC_EN BIT(24)
  18. +#define A_SSC_PERI BIT(19)
  19. +#define A_SSC_GEN BIT(18)
  20. +#define A_SSC_M 0x3
  21. +#define A_SSC_S 16
  22. +#define A_DLY_M 0x7
  23. +#define A_DLY_S 8
  24. +#define A_VTUNE_M 0xff
  25. +
  26. +/* digital */
  27. +#define PMU1_CFG 0x8C
  28. +#define DIG_SW_SEL BIT(25)
  29. +
  30. /* does the board have sdram or ddram */
  31. static int dram_type;
  32. @@ -339,6 +355,8 @@ void prom_soc_init(struct ralink_soc_inf
  33. u32 n1;
  34. u32 rev;
  35. u32 cfg0;
  36. + u32 pmu0;
  37. + u32 pmu1;
  38. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  39. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  40. @@ -386,4 +404,12 @@ void prom_soc_init(struct ralink_soc_inf
  41. BUG();
  42. }
  43. soc_info->mem_base = MT7620_DRAM_BASE;
  44. +
  45. + pmu0 = __raw_readl(sysc + PMU0_CFG);
  46. + pmu1 = __raw_readl(sysc + PMU1_CFG);
  47. +
  48. + pr_info("Analog PMU set to %s control\n",
  49. + (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
  50. + pr_info("Digital PMU set to %s control\n",
  51. + (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
  52. }