rt3352.dtsi 4.8 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,rt3352-soc";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24KEc";
  8. };
  9. };
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. cpuintc: cpuintc@0 {
  14. #address-cells = <0>;
  15. #interrupt-cells = <1>;
  16. interrupt-controller;
  17. compatible = "mti,cpu-interrupt-controller";
  18. };
  19. palmbus@10000000 {
  20. compatible = "palmbus";
  21. reg = <0x10000000 0x200000>;
  22. ranges = <0x0 0x10000000 0x1FFFFF>;
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. sysc@0 {
  26. compatible = "ralink,rt3352-sysc", "ralink,rt3050-sysc";
  27. reg = <0x0 0x100>;
  28. };
  29. timer@100 {
  30. compatible = "ralink,rt3352-timer", "ralink,rt2880-timer";
  31. reg = <0x100 0x20>;
  32. interrupt-parent = <&intc>;
  33. interrupts = <1>;
  34. };
  35. watchdog@120 {
  36. compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt";
  37. reg = <0x120 0x10>;
  38. resets = <&rstctrl 8>;
  39. reset-names = "wdt";
  40. interrupt-parent = <&intc>;
  41. interrupts = <1>;
  42. };
  43. intc: intc@200 {
  44. compatible = "ralink,rt3352-intc", "ralink,rt2880-intc";
  45. reg = <0x200 0x100>;
  46. interrupt-controller;
  47. #interrupt-cells = <1>;
  48. interrupt-parent = <&cpuintc>;
  49. interrupts = <2>;
  50. };
  51. memc@300 {
  52. compatible = "ralink,rt3352-memc", "ralink,rt3050-memc";
  53. reg = <0x300 0x100>;
  54. resets = <&rstctrl 20>;
  55. reset-names = "mc";
  56. interrupt-parent = <&intc>;
  57. interrupts = <3>;
  58. };
  59. uart@500 {
  60. compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
  61. reg = <0x500 0x100>;
  62. resets = <&rstctrl 12>;
  63. reset-names = "uart";
  64. interrupt-parent = <&intc>;
  65. interrupts = <5>;
  66. reg-shift = <2>;
  67. status = "disabled";
  68. };
  69. gpio0: gpio@600 {
  70. compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
  71. reg = <0x600 0x34>;
  72. gpio-controller;
  73. #gpio-cells = <2>;
  74. ralink,gpio-base = <0>;
  75. ralink,num-gpios = <24>;
  76. ralink,register-map = [ 00 04 08 0c
  77. 20 24 28 2c
  78. 30 34 ];
  79. resets = <&rstctrl 13>;
  80. reset-names = "pio";
  81. interrupt-parent = <&intc>;
  82. interrupts = <6>;
  83. };
  84. gpio1: gpio@638 {
  85. compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
  86. reg = <0x638 0x24>;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. ralink,gpio-base = <24>;
  90. ralink,num-gpios = <16>;
  91. ralink,register-map = [ 00 04 08 0c
  92. 10 14 18 1c
  93. 20 24 ];
  94. status = "disabled";
  95. };
  96. gpio2: gpio@660 {
  97. compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
  98. reg = <0x660 0x24>;
  99. gpio-controller;
  100. #gpio-cells = <2>;
  101. ralink,gpio-base = <40>;
  102. ralink,num-gpios = <6>;
  103. ralink,register-map = [ 00 04 08 0c
  104. 10 14 18 1c
  105. 20 24 ];
  106. status = "disabled";
  107. };
  108. spi@b00 {
  109. compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
  110. reg = <0xb00 0x100>;
  111. #address-cells = <1>;
  112. #size-cells = <1>;
  113. resets = <&rstctrl 18>;
  114. reset-names = "spi";
  115. pinctrl-names = "default";
  116. pinctrl-0 = <&spi_pins>;
  117. status = "disabled";
  118. };
  119. uartlite@c00 {
  120. compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
  121. reg = <0xc00 0x100>;
  122. resets = <&rstctrl 19>;
  123. reset-names = "uartl";
  124. interrupt-parent = <&intc>;
  125. interrupts = <12>;
  126. reg-shift = <2>;
  127. pinctrl-names = "default";
  128. pinctrl-0 = <&uartlite_pins>;
  129. };
  130. };
  131. pinctrl {
  132. compatible = "ralink,rt2880-pinmux";
  133. pinctrl-names = "default";
  134. pinctrl-0 = <&state_default>;
  135. state_default: pinctrl0 {
  136. };
  137. spi_pins: spi {
  138. spi {
  139. ralink,group = "spi";
  140. ralink,function = "spi";
  141. };
  142. };
  143. uartlite_pins: uartlite {
  144. uart {
  145. ralink,group = "uartlite";
  146. ralink,function = "uartlite";
  147. };
  148. };
  149. };
  150. rstctrl: rstctrl {
  151. compatible = "ralink,rt3352-reset", "ralink,rt2880-reset";
  152. #reset-cells = <1>;
  153. };
  154. ethernet@10100000 {
  155. compatible = "ralink,rt3352-eth", "ralink,rt3050-eth";
  156. reg = <0x10100000 10000>;
  157. resets = <&rstctrl 21>;
  158. reset-names = "fe";
  159. interrupt-parent = <&cpuintc>;
  160. interrupts = <5>;
  161. };
  162. esw@10110000 {
  163. compatible = "ralink,rt3352-esw", "ralink,rt3050-esw";
  164. reg = <0x10110000 8000>;
  165. resets = <&rstctrl 23>;
  166. reset-names = "esw";
  167. interrupt-parent = <&intc>;
  168. interrupts = <17>;
  169. };
  170. usbphy: usbphy {
  171. compatible = "ralink,rt3xxx-usbphy";
  172. #phy-cells = <1>;
  173. resets = <&rstctrl 22 &rstctrl 25>;
  174. reset-names = "host", "device";
  175. };
  176. wmac@10180000 {
  177. compatible = "ralink,rt3352-wmac", "ralink,rt2880-wmac";
  178. reg = <0x10180000 40000>;
  179. interrupt-parent = <&cpuintc>;
  180. interrupts = <6>;
  181. ralink,eeprom = "soc_wmac.eeprom";
  182. };
  183. ehci@101c0000 {
  184. compatible = "ralink,rt3xxx-ehci", "ehci-platform";
  185. reg = <0x101c0000 0x1000>;
  186. phys = <&usbphy 1>;
  187. phy-names = "usb";
  188. interrupt-parent = <&intc>;
  189. interrupts = <18>;
  190. status = "disabled";
  191. };
  192. ohci@101c1000 {
  193. compatible = "ralink,rt3xxx-ohci", "ohci-platform";
  194. reg = <0x101c1000 0x1000>;
  195. phys = <&usbphy 1>;
  196. phy-names = "usb";
  197. interrupt-parent = <&intc>;
  198. interrupts = <18>;
  199. status = "disabled";
  200. };
  201. };