rt3050.dtsi 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257
  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,rt3050-soc", "ralink,rt3052-soc", "ralink,rt3350-soc";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24KEc";
  8. };
  9. };
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. cpuintc: cpuintc@0 {
  14. #address-cells = <0>;
  15. #interrupt-cells = <1>;
  16. interrupt-controller;
  17. compatible = "mti,cpu-interrupt-controller";
  18. };
  19. palmbus@10000000 {
  20. compatible = "palmbus";
  21. reg = <0x10000000 0x200000>;
  22. ranges = <0x0 0x10000000 0x1FFFFF>;
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. sysc@0 {
  26. compatible = "ralink,rt3050-sysc";
  27. reg = <0x0 0x100>;
  28. };
  29. timer@100 {
  30. compatible = "ralink,rt3050-timer", "ralink,rt2880-timer";
  31. reg = <0x100 0x20>;
  32. interrupt-parent = <&intc>;
  33. interrupts = <1>;
  34. };
  35. watchdog@120 {
  36. compatible = "ralink,rt3050-wdt", "ralink,rt2880-wdt";
  37. reg = <0x120 0x10>;
  38. resets = <&rstctrl 8>;
  39. reset-names = "wdt";
  40. interrupt-parent = <&intc>;
  41. interrupts = <1>;
  42. };
  43. intc: intc@200 {
  44. compatible = "ralink,rt3050-intc", "ralink,rt2880-intc";
  45. reg = <0x200 0x100>;
  46. resets = <&rstctrl 19>;
  47. reset-names = "intc";
  48. interrupt-controller;
  49. #interrupt-cells = <1>;
  50. interrupt-parent = <&cpuintc>;
  51. interrupts = <2>;
  52. };
  53. memc@300 {
  54. compatible = "ralink,rt3050-memc";
  55. reg = <0x300 0x100>;
  56. resets = <&rstctrl 20>;
  57. reset-names = "mc";
  58. interrupt-parent = <&intc>;
  59. interrupts = <3>;
  60. };
  61. uart@500 {
  62. compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
  63. reg = <0x500 0x100>;
  64. resets = <&rstctrl 12>;
  65. reset-names = "uart";
  66. interrupt-parent = <&intc>;
  67. interrupts = <5>;
  68. reg-shift = <2>;
  69. status = "disabled";
  70. };
  71. gpio0: gpio@600 {
  72. compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
  73. reg = <0x600 0x34>;
  74. gpio-controller;
  75. #gpio-cells = <2>;
  76. ralink,gpio-base = <0>;
  77. ralink,num-gpios = <24>;
  78. ralink,register-map = [ 00 04 08 0c
  79. 20 24 28 2c
  80. 30 34 ];
  81. resets = <&rstctrl 13>;
  82. reset-names = "pio";
  83. interrupt-parent = <&intc>;
  84. interrupts = <6>;
  85. };
  86. gpio1: gpio@638 {
  87. compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
  88. reg = <0x638 0x24>;
  89. gpio-controller;
  90. #gpio-cells = <2>;
  91. ralink,gpio-base = <24>;
  92. ralink,num-gpios = <16>;
  93. ralink,register-map = [ 00 04 08 0c
  94. 10 14 18 1c
  95. 20 24 ];
  96. status = "disabled";
  97. };
  98. gpio2: gpio@660 {
  99. compatible = "ralink,rt3050-gpio", "ralink,rt2880-gpio";
  100. reg = <0x660 0x24>;
  101. gpio-controller;
  102. #gpio-cells = <2>;
  103. ralink,gpio-base = <40>;
  104. ralink,num-gpios = <12>;
  105. ralink,register-map = [ 00 04 08 0c
  106. 10 14 18 1c
  107. 20 24 ];
  108. status = "disabled";
  109. };
  110. spi@b00 {
  111. compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
  112. reg = <0xb00 0x100>;
  113. resets = <&rstctrl 18>;
  114. reset-names = "spi";
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. pinctrl-names = "default";
  118. pinctrl-0 = <&spi_pins>;
  119. status = "disabled";
  120. };
  121. uartlite@c00 {
  122. compatible = "ralink,rt3050-uart", "ralink,rt2880-uart", "ns16550a";
  123. reg = <0xc00 0x100>;
  124. resets = <&rstctrl 19>;
  125. reset-names = "uartl";
  126. interrupt-parent = <&intc>;
  127. interrupts = <12>;
  128. reg-shift = <2>;
  129. pinctrl-names = "default";
  130. pinctrl-0 = <&uartlite_pins>;
  131. };
  132. };
  133. pinctrl {
  134. compatible = "ralink,rt2880-pinmux";
  135. pinctrl-names = "default";
  136. pinctrl-0 = <&state_default>;
  137. state_default: pinctrl0 {
  138. sdram {
  139. ralink,group = "sdram";
  140. ralink,function = "sdram";
  141. };
  142. };
  143. spi_pins: spi {
  144. spi {
  145. ralink,group = "spi";
  146. ralink,function = "spi";
  147. };
  148. };
  149. uartlite_pins: uartlite {
  150. uart {
  151. ralink,group = "uartlite";
  152. ralink,function = "uartlite";
  153. };
  154. };
  155. };
  156. rstctrl: rstctrl {
  157. compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
  158. #reset-cells = <1>;
  159. };
  160. ethernet@10100000 {
  161. compatible = "ralink,rt3050-eth";
  162. reg = <0x10100000 10000>;
  163. resets = <&rstctrl 21>;
  164. reset-names = "fe";
  165. interrupt-parent = <&cpuintc>;
  166. interrupts = <5>;
  167. };
  168. esw@10110000 {
  169. compatible = "ralink,rt3050-esw";
  170. reg = <0x10110000 8000>;
  171. resets = <&rstctrl 23>;
  172. reset-names = "esw";
  173. interrupt-parent = <&intc>;
  174. interrupts = <17>;
  175. };
  176. wmac@10180000 {
  177. compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
  178. reg = <0x10180000 40000>;
  179. interrupt-parent = <&cpuintc>;
  180. interrupts = <6>;
  181. ralink,eeprom = "soc_wmac.eeprom";
  182. };
  183. otg@101c0000 {
  184. compatible = "ralink,rt3050-otg", "snps,dwc2";
  185. reg = <0x101c0000 40000>;
  186. interrupt-parent = <&intc>;
  187. interrupts = <18>;
  188. resets = <&rstctrl 22>;
  189. reset-names = "otg";
  190. status = "disabled";
  191. };
  192. };