mt7628an.dtsi 7.4 KB

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  1. / {
  2. #address-cells = <1>;
  3. #size-cells = <1>;
  4. compatible = "ralink,mtk7628an-soc";
  5. cpus {
  6. cpu@0 {
  7. compatible = "mips,mips24KEc";
  8. };
  9. };
  10. chosen {
  11. bootargs = "console=ttyS0,57600";
  12. };
  13. cpuintc: cpuintc@0 {
  14. compatible = "mti,cpu-interrupt-controller";
  15. interrupt-controller;
  16. #interrupt-cells = <1>;
  17. };
  18. palmbus@10000000 {
  19. compatible = "palmbus";
  20. reg = <0x10000000 0x200000>;
  21. ranges = <0x0 0x10000000 0x1FFFFF>;
  22. #address-cells = <1>;
  23. #size-cells = <1>;
  24. sysc@0 {
  25. compatible = "ralink,mt7620a-sysc";
  26. reg = <0x0 0x100>;
  27. };
  28. watchdog@120 {
  29. compatible = "ralink,mt7628an-wdt", "mtk,mt7621-wdt";
  30. reg = <0x120 0x10>;
  31. resets = <&rstctrl 8>;
  32. reset-names = "wdt";
  33. interrupt-parent = <&intc>;
  34. interrupts = <24>;
  35. };
  36. intc: intc@200 {
  37. compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
  38. reg = <0x200 0x100>;
  39. resets = <&rstctrl 9>;
  40. reset-names = "intc";
  41. interrupt-controller;
  42. #interrupt-cells = <1>;
  43. interrupt-parent = <&cpuintc>;
  44. interrupts = <2>;
  45. ralink,intc-registers = <0x9c 0xa0
  46. 0x6c 0xa4
  47. 0x80 0x78>;
  48. };
  49. memc@300 {
  50. compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  51. reg = <0x300 0x100>;
  52. resets = <&rstctrl 20>;
  53. reset-names = "mc";
  54. interrupt-parent = <&intc>;
  55. interrupts = <3>;
  56. };
  57. gpio@600 {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  61. reg = <0x600 0x100>;
  62. interrupt-parent = <&intc>;
  63. interrupts = <6>;
  64. gpio0: bank@0 {
  65. reg = <0>;
  66. compatible = "mtk,mt7621-gpio-bank";
  67. gpio-controller;
  68. #gpio-cells = <2>;
  69. };
  70. gpio1: bank@1 {
  71. reg = <1>;
  72. compatible = "mtk,mt7621-gpio-bank";
  73. gpio-controller;
  74. #gpio-cells = <2>;
  75. };
  76. gpio2: bank@2 {
  77. reg = <2>;
  78. compatible = "mtk,mt7621-gpio-bank";
  79. gpio-controller;
  80. #gpio-cells = <2>;
  81. };
  82. };
  83. i2c@900 {
  84. compatible = "mediatek,mt7628-i2c";
  85. reg = <0x900 0x100>;
  86. resets = <&rstctrl 16>;
  87. reset-names = "i2c";
  88. #address-cells = <1>;
  89. #size-cells = <0>;
  90. status = "disabled";
  91. pinctrl-names = "default";
  92. pinctrl-0 = <&i2c_pins>;
  93. };
  94. i2s@a00 {
  95. compatible = "ralink,mt7620a-i2s";
  96. reg = <0xa00 0x100>;
  97. resets = <&rstctrl 17>;
  98. reset-names = "i2s";
  99. interrupt-parent = <&intc>;
  100. interrupts = <10>;
  101. dmas = <&gdma 2>,
  102. <&gdma 3>;
  103. dma-names = "tx", "rx";
  104. status = "disabled";
  105. };
  106. spi@b00 {
  107. compatible = "ralink,mt7621-spi";
  108. reg = <0xb00 0x100>;
  109. resets = <&rstctrl 18>;
  110. reset-names = "spi";
  111. #address-cells = <1>;
  112. #size-cells = <1>;
  113. pinctrl-names = "default";
  114. pinctrl-0 = <&spi_pins>;
  115. status = "disabled";
  116. };
  117. uartlite@c00 {
  118. compatible = "ns16550a";
  119. reg = <0xc00 0x100>;
  120. reg-shift = <2>;
  121. reg-io-width = <4>;
  122. no-loopback-test;
  123. resets = <&rstctrl 12>;
  124. reset-names = "uartl";
  125. interrupt-parent = <&intc>;
  126. interrupts = <20>;
  127. pinctrl-names = "default";
  128. pinctrl-0 = <&uart0_pins>;
  129. };
  130. uart1@d00 {
  131. compatible = "ns16550a";
  132. reg = <0xd00 0x100>;
  133. reg-shift = <2>;
  134. reg-io-width = <4>;
  135. no-loopback-test;
  136. resets = <&rstctrl 19>;
  137. reset-names = "uart1";
  138. interrupt-parent = <&intc>;
  139. interrupts = <21>;
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&uart1_pins>;
  142. status = "disabled";
  143. };
  144. uart2@e00 {
  145. compatible = "ns16550a";
  146. reg = <0xe00 0x100>;
  147. reg-shift = <2>;
  148. reg-io-width = <4>;
  149. no-loopback-test;
  150. resets = <&rstctrl 20>;
  151. reset-names = "uart2";
  152. interrupt-parent = <&intc>;
  153. interrupts = <22>;
  154. pinctrl-names = "default";
  155. pinctrl-0 = <&uart2_pins>;
  156. status = "disabled";
  157. };
  158. pwm@5000 {
  159. compatible = "mediatek,mt7628-pwm";
  160. reg = <0x5000 0x1000>;
  161. resets = <&rstctrl 31>;
  162. reset-names = "pwm";
  163. pinctrl-names = "default";
  164. pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
  165. status = "disabled";
  166. };
  167. pcm@2000 {
  168. compatible = "ralink,mt7620a-pcm";
  169. reg = <0x2000 0x800>;
  170. resets = <&rstctrl 11>;
  171. reset-names = "pcm";
  172. interrupt-parent = <&intc>;
  173. interrupts = <4>;
  174. status = "disabled";
  175. };
  176. gdma: gdma@2800 {
  177. compatible = "ralink,mt7620a-gdma", "ralink,rt2880-gdma";
  178. reg = <0x2800 0x800>;
  179. resets = <&rstctrl 14>;
  180. reset-names = "dma";
  181. interrupt-parent = <&intc>;
  182. interrupts = <7>;
  183. #dma-cells = <1>;
  184. #dma-channels = <16>;
  185. #dma-requests = <16>;
  186. status = "disabled";
  187. };
  188. };
  189. pinctrl {
  190. compatible = "ralink,rt2880-pinmux";
  191. pinctrl-names = "default";
  192. pinctrl-0 = <&state_default>;
  193. state_default: pinctrl0 {
  194. };
  195. spi_pins: spi {
  196. spi {
  197. ralink,group = "spi";
  198. ralink,function = "spi";
  199. };
  200. };
  201. spi_cs1_pins: spi_cs1 {
  202. spi_cs1 {
  203. ralink,group = "spi cs1";
  204. ralink,function = "spi cs1";
  205. };
  206. };
  207. i2c_pins: i2c {
  208. i2c {
  209. ralink,group = "i2c";
  210. ralink,function = "i2c";
  211. };
  212. };
  213. uart0_pins: uartlite {
  214. uartlite {
  215. ralink,group = "uart0";
  216. ralink,function = "uart0";
  217. };
  218. };
  219. uart1_pins: uart1 {
  220. uart1 {
  221. ralink,group = "uart1";
  222. ralink,function = "uart1";
  223. };
  224. };
  225. uart2_pins: uart2 {
  226. uart2 {
  227. ralink,group = "uart2";
  228. ralink,function = "uart2";
  229. };
  230. };
  231. sdxc_pins: sdxc {
  232. sdxc {
  233. ralink,group = "sdmode";
  234. ralink,function = "sdxc";
  235. };
  236. };
  237. pwm0_pins: pwm0 {
  238. pwm0 {
  239. ralink,group = "pwm0";
  240. ralink,function = "pwm0";
  241. };
  242. };
  243. pwm1_pins: pwm1 {
  244. pwm1 {
  245. ralink,group = "pwm1";
  246. ralink,function = "pwm1";
  247. };
  248. };
  249. pcm_i2s_pins: i2s {
  250. i2s {
  251. ralink,group = "i2s";
  252. ralink,function = "pcm";
  253. };
  254. };
  255. };
  256. rstctrl: rstctrl {
  257. compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
  258. #reset-cells = <1>;
  259. };
  260. usbphy: usbphy@10120000 {
  261. compatible = "ralink,mt7628an-usbphy", "ralink,mt7620a-usbphy";
  262. reg = <0x10120000 1000>;
  263. #phy-cells = <1>;
  264. resets = <&rstctrl 22 &rstctrl 25>;
  265. reset-names = "host", "device";
  266. };
  267. sdhci@10130000 {
  268. compatible = "ralink,mt7620-sdhci";
  269. reg = <0x10130000 4000>;
  270. interrupt-parent = <&intc>;
  271. interrupts = <14>;
  272. pinctrl-names = "default";
  273. pinctrl-0 = <&sdxc_pins>;
  274. status = "disabled";
  275. };
  276. ehci@101c0000 {
  277. compatible = "ralink,rt3xxx-ehci";
  278. reg = <0x101c0000 0x1000>;
  279. phys = <&usbphy 1>;
  280. phy-names = "usb";
  281. interrupt-parent = <&intc>;
  282. interrupts = <18>;
  283. };
  284. ohci@101c1000 {
  285. compatible = "ralink,rt3xxx-ohci";
  286. reg = <0x101c1000 0x1000>;
  287. phys = <&usbphy 1>;
  288. phy-names = "usb";
  289. interrupt-parent = <&intc>;
  290. interrupts = <18>;
  291. };
  292. ethernet@10100000 {
  293. compatible = "ralink,rt5350-eth";
  294. reg = <0x10100000 10000>;
  295. interrupt-parent = <&cpuintc>;
  296. interrupts = <5>;
  297. resets = <&rstctrl 21 &rstctrl 23>;
  298. reset-names = "fe", "esw";
  299. };
  300. esw@10110000 {
  301. compatible = "ralink,rt3050-esw";
  302. reg = <0x10110000 8000>;
  303. resets = <&rstctrl 23>;
  304. reset-names = "esw";
  305. interrupt-parent = <&intc>;
  306. interrupts = <17>;
  307. };
  308. pcie@10140000 {
  309. compatible = "mediatek,mt7620-pci";
  310. reg = <0x10140000 0x100
  311. 0x10142000 0x100>;
  312. #address-cells = <3>;
  313. #size-cells = <2>;
  314. resets = <&rstctrl 26>;
  315. reset-names = "pcie0";
  316. interrupt-parent = <&cpuintc>;
  317. interrupts = <4>;
  318. status = "disabled";
  319. device_type = "pci";
  320. bus-range = <0 255>;
  321. ranges = <
  322. 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
  323. 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
  324. >;
  325. pcie-bridge {
  326. reg = <0x0000 0 0 0 0>;
  327. #address-cells = <3>;
  328. #size-cells = <2>;
  329. device_type = "pci";
  330. };
  331. };
  332. };