MT7620a_V22SG.dts 1.7 KB

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  1. /dts-v1/;
  2. /include/ "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  5. model = "Ralink MT7620a V22SG High Power evaluation board";
  6. /*palmbus@10000000 {
  7. };*/
  8. pinctrl {
  9. state_default: pinctrl0 {
  10. gpio {
  11. ralink,group = "i2c", "uartf", "spi";
  12. ralink,function = "gpio";
  13. };
  14. };
  15. };
  16. ethernet@10100000 {
  17. status = "okay";
  18. pinctrl-names = "default";
  19. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  20. ralink,port-map = "llllw";
  21. port@4 {
  22. status = "okay";
  23. phy-handle = <&phy4>;
  24. phy-mode = "rgmii";
  25. };
  26. port@5 {
  27. status = "okay";
  28. phy-handle = <&phy5>;
  29. phy-mode = "rgmii";
  30. };
  31. mdio-bus {
  32. status = "okay";
  33. phy4: ethernet-phy@4 {
  34. reg = <4>;
  35. phy-mode = "rgmii";
  36. };
  37. phy5: ethernet-phy@5 {
  38. reg = <5>;
  39. phy-mode = "rgmii";
  40. };
  41. };
  42. };
  43. gsw@10110000 {
  44. ralink,port4 = "gmac";
  45. };
  46. pcie@10140000 {
  47. status = "okay";
  48. };
  49. ehci@101c0000 {
  50. status = "okay";
  51. };
  52. ohci@101c1000 {
  53. status = "okay";
  54. };
  55. gpio-keys-polled {
  56. compatible = "gpio-keys-polled";
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. poll-interval = <20>;
  60. reset {
  61. label = "reset";
  62. gpios = <&gpio0 1 1>;
  63. linux,code = <0x198>;
  64. };
  65. aoss {
  66. label = "aoss";
  67. gpios = <&gpio0 2 1>;
  68. linux,code = <0x211>;
  69. };
  70. };
  71. nand {
  72. #address-cells = <1>;
  73. #size-cells = <1>;
  74. compatible = "mtk,mt7620-nand";
  75. partition@0 {
  76. label = "u-boot";
  77. reg = <0x0 0x40000>;
  78. read-only;
  79. };
  80. partition@40000 {
  81. label = "u-boot-env";
  82. reg = <0x40000 0x20000>;
  83. read-only;
  84. };
  85. factory: partition@60000 {
  86. label = "factory";
  87. reg = <0x60000 0x20000>;
  88. read-only;
  89. };
  90. partition@80000 {
  91. label = "firmware";
  92. reg = <0x80000 0x7f80000>;
  93. };
  94. };
  95. };