P2812HNUFX.dtsi 5.8 KB

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  1. /include/ "vr9.dtsi"
  2. / {
  3. chosen {
  4. bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
  5. };
  6. memory@0 {
  7. reg = <0x0 0x8000000>;
  8. };
  9. fpi@10000000 {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "lantiq,fpi", "simple-bus";
  13. ranges = <0x0 0x10000000 0xEEFFFFF>;
  14. reg = <0x10000000 0xEF00000>;
  15. localbus@0 {
  16. #address-cells = <2>;
  17. #size-cells = <1>;
  18. ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
  19. 1 0 0x4000000 0x4000010>; /* addsel1 */
  20. compatible = "lantiq,localbus", "simple-bus";
  21. };
  22. gpio: pinmux@E100B10 {
  23. compatible = "lantiq,pinctrl-xr9";
  24. pinctrl-names = "default";
  25. pinctrl-0 = <&state_default>;
  26. interrupt-parent = <&icu0>;
  27. interrupts = <166 135 66 40 41 42 38>;
  28. #gpio-cells = <2>;
  29. gpio-controller;
  30. reg = <0xE100B10 0xA0>;
  31. state_default: pinmux {
  32. exin3 {
  33. lantiq,groups = "exin3";
  34. lantiq,function = "exin";
  35. };
  36. mdio {
  37. lantiq,groups = "mdio";
  38. lantiq,function = "mdio";
  39. };
  40. gphy-leds {
  41. lantiq,groups = "gphy0 led1", "gphy1 led1",
  42. "gphy0 led2", "gphy1 led2";
  43. lantiq,function = "gphy";
  44. lantiq,pull = <2>;
  45. lantiq,open-drain = <0>;
  46. lantiq,output = <1>;
  47. };
  48. stp {
  49. lantiq,groups = "stp";
  50. lantiq,function = "stp";
  51. lantiq,pull = <2>;
  52. lantiq,open-drain = <0>;
  53. lantiq,output = <1>;
  54. };
  55. pci-in {
  56. lantiq,groups = "req1";
  57. lantiq,function = "pci";
  58. lantiq,output = <0>;
  59. lantiq,open-drain = <1>;
  60. lantiq,pull = <2>;
  61. };
  62. pci-out {
  63. lantiq,groups = "gnt1";
  64. lantiq,function = "pci";
  65. lantiq,output = <1>;
  66. lantiq,open-drain = <0>;
  67. lantiq,pull = <0>;
  68. };
  69. pci_rst {
  70. lantiq,pins = "io21";
  71. lantiq,output = <1>;
  72. lantiq,open-drain = <0>;
  73. lantiq,pull = <2>;
  74. };
  75. pcie-rst {
  76. lantiq,pins = "io38";
  77. lantiq,pull = <0>;
  78. lantiq,output = <1>;
  79. };
  80. ifxhcd-rst {
  81. lantiq,pins = "io33";
  82. lantiq,pull = <0>;
  83. lantiq,open-drain = <0>;
  84. lantiq,output = <1>;
  85. };
  86. nand_out {
  87. lantiq,groups = "nand cle", "nand ale";
  88. lantiq,function = "ebu";
  89. lantiq,output = <1>;
  90. lantiq,open-drain = <0>;
  91. lantiq,pull = <0>;
  92. };
  93. nand_cs1 {
  94. lantiq,groups = "nand cs1";
  95. lantiq,function = "ebu";
  96. lantiq,open-drain = <0>;
  97. lantiq,pull = <0>;
  98. };
  99. };
  100. };
  101. eth@E108000 {
  102. #address-cells = <1>;
  103. #size-cells = <0>;
  104. compatible = "lantiq,xrx200-net";
  105. reg = < 0xE108000 0x3000 /* switch */
  106. 0xE10B100 0x70 /* mdio */
  107. 0xE10B1D8 0x30 /* mii */
  108. 0xE10B308 0x30 >; /* pmac */
  109. interrupt-parent = <&icu0>;
  110. interrupts = <73 72>;
  111. lan: interface@0 {
  112. compatible = "lantiq,xrx200-pdi";
  113. #address-cells = <1>;
  114. #size-cells = <0>;
  115. reg = <0>;
  116. mac-address = [ 00 11 22 33 44 55 ];
  117. lantiq,switch;
  118. ethernet@0 {
  119. compatible = "lantiq,xrx200-pdi-port";
  120. reg = <0>;
  121. phy-mode = "rgmii";
  122. phy-handle = <&phy0>;
  123. };
  124. ethernet@1 {
  125. compatible = "lantiq,xrx200-pdi-port";
  126. reg = <1>;
  127. phy-mode = "rgmii";
  128. phy-handle = <&phy1>;
  129. };
  130. ethernet@2 {
  131. compatible = "lantiq,xrx200-pdi-port";
  132. reg = <2>;
  133. phy-mode = "gmii";
  134. phy-handle = <&phy11>;
  135. };
  136. ethernet@4 {
  137. compatible = "lantiq,xrx200-pdi-port";
  138. reg = <4>;
  139. phy-mode = "gmii";
  140. phy-handle = <&phy13>;
  141. };
  142. ethernet@5 {
  143. compatible = "lantiq,xrx200-pdi-port";
  144. reg = <5>;
  145. phy-mode = "rgmii";
  146. phy-handle = <&phy5>;
  147. };
  148. };
  149. mdio@0 {
  150. #address-cells = <1>;
  151. #size-cells = <0>;
  152. compatible = "lantiq,xrx200-mdio";
  153. phy0: ethernet-phy@0 {
  154. reg = <0x0>;
  155. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  156. };
  157. phy1: ethernet-phy@1 {
  158. reg = <0x1>;
  159. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  160. };
  161. phy5: ethernet-phy@5 {
  162. reg = <0x5>;
  163. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  164. };
  165. phy11: ethernet-phy@11 {
  166. reg = <0x11>;
  167. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  168. };
  169. phy13: ethernet-phy@13 {
  170. reg = <0x13>;
  171. compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  172. };
  173. };
  174. };
  175. stp: stp@E100BB0 {
  176. compatible = "lantiq,gpio-stp-xway";
  177. reg = <0xE100BB0 0x40>;
  178. #gpio-cells = <2>;
  179. gpio-controller;
  180. lantiq,shadow = <0xffffff>;
  181. lantiq,groups = <0x7>;
  182. lantiq,dsl = <0x0>;
  183. lantiq,phy1 = <0x0>;
  184. lantiq,phy2 = <0x0>;
  185. };
  186. ifxhcd@E101000 {
  187. status = "okay";
  188. gpios = <&gpio 33 0>;
  189. lantiq,portmask = <0x3>;
  190. };
  191. ifxhcd@E106000 {
  192. status = "okay";
  193. gpios = <&gpio 33 0>;
  194. };
  195. pci@E105400 {
  196. status = "okay";
  197. #address-cells = <3>;
  198. #size-cells = <2>;
  199. #interrupt-cells = <1>;
  200. compatible = "lantiq,pci-xway";
  201. bus-range = <0x0 0x0>;
  202. ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
  203. 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
  204. reg = <0x7000000 0x8000 /* config space */
  205. 0xE105400 0x400>; /* pci bridge */
  206. lantiq,bus-clock = <33333333>;
  207. /*lantiq,external-clock;*/
  208. lantiq,delay-hi = <0>; /* 0ns delay */
  209. lantiq,delay-lo = <0>; /* 0.0ns delay */
  210. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  211. interrupt-map = <
  212. 0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30
  213. >;
  214. gpio-reset = <&gpio 21 0>;
  215. req-mask = <0x1>; /* GNT1 */
  216. };
  217. };
  218. gphy-xrx200 {
  219. compatible = "lantiq,phy-xrx200";
  220. firmware1 = "lantiq/vr9_phy11g_a1x.bin"; /*VR9 1.1*/
  221. firmware2 = "lantiq/vr9_phy11g_a2x.bin"; /*VR9 1.2*/
  222. phys = [ 00 01 ];
  223. };
  224. gpio-keys-polled {
  225. compatible = "gpio-keys-polled";
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228. poll-interval = <100>;
  229. reset {
  230. label = "reset";
  231. gpios = <&gpio 39 1>;
  232. linux,code = <0x198>;
  233. };
  234. rfkill {
  235. label = "rfkill";
  236. gpios = <&gpio 1 1>;
  237. linux,code = <0xf7>;
  238. };
  239. };
  240. };