021-ARM-mvebu-Add-Armada-385-Access-Point-Development-Bo.patch 5.7 KB

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  1. From e5ee12817e9eac891c6b2a340f64d94d9abd355f Mon Sep 17 00:00:00 2001
  2. From: Maxime Ripard <maxime.ripard@free-electrons.com>
  3. Date: Thu, 8 Jan 2015 18:38:09 +0100
  4. Subject: [PATCH 4/4] ARM: mvebu: Add Armada 385 Access Point Development Board
  5. support
  6. The A385-AP is a board produced by Marvell that holds 3 mPCIe slot, a 16MB
  7. SPI-NOR, 3 Gigabit Ethernet ports, USB3 and NAND flash storage.
  8. [gregory.clement@free-electrons.com: switch the license to the dual
  9. X11/GPL with the agreement of the author]
  10. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
  12. Signed-off-by: Andrew Lunn <andrew@lunn.ch>
  13. ---
  14. arch/arm/boot/dts/Makefile | 1 +
  15. arch/arm/boot/dts/armada-385-db-ap.dts | 178 +++++++++++++++++++++++++++++++++
  16. 2 files changed, 179 insertions(+)
  17. create mode 100644 arch/arm/boot/dts/armada-385-db-ap.dts
  18. --- a/arch/arm/boot/dts/Makefile
  19. +++ b/arch/arm/boot/dts/Makefile
  20. @@ -500,6 +500,7 @@ dtb-$(CONFIG_MACH_ARMADA_375) += \
  21. armada-375-db.dtb
  22. dtb-$(CONFIG_MACH_ARMADA_38X) += \
  23. armada-385-db.dtb \
  24. + armada-385-db-ap.dtb \
  25. armada-385-rd.dtb
  26. dtb-$(CONFIG_MACH_ARMADA_XP) += \
  27. armada-xp-axpwifiap.dtb \
  28. --- /dev/null
  29. +++ b/arch/arm/boot/dts/armada-385-db-ap.dts
  30. @@ -0,0 +1,178 @@
  31. +/*
  32. + * Device Tree file for Marvell Armada 385 Access Point Development board
  33. + * (DB-88F6820-AP)
  34. + *
  35. + * Copyright (C) 2014 Marvell
  36. + *
  37. + * Nadav Haklai <nadavh@marvell.com>
  38. + *
  39. + * This file is dual-licensed: you can use it either under the terms
  40. + * of the GPL or the X11 license, at your option. Note that this dual
  41. + * licensing only applies to this file, and not this project as a
  42. + * whole.
  43. + *
  44. + * a) This file is licensed under the terms of the GNU General Public
  45. + * License version 2. This program is licensed "as is" without
  46. + * any warranty of any kind, whether express or implied.
  47. + *
  48. + * Or, alternatively,
  49. + *
  50. + * b) Permission is hereby granted, free of charge, to any person
  51. + * obtaining a copy of this software and associated documentation
  52. + * files (the "Software"), to deal in the Software without
  53. + * restriction, including without limitation the rights to use,
  54. + * copy, modify, merge, publish, distribute, sublicense, and/or
  55. + * sell copies of the Software, and to permit persons to whom the
  56. + * Software is furnished to do so, subject to the following
  57. + * conditions:
  58. + *
  59. + * The above copyright notice and this permission notice shall be
  60. + * included in all copies or substantial portions of the Software.
  61. + *
  62. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  63. + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  64. + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  65. + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  66. + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  67. + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  68. + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  69. + * OTHER DEALINGS IN THE SOFTWARE.
  70. + */
  71. +
  72. +/dts-v1/;
  73. +#include "armada-385.dtsi"
  74. +
  75. +#include <dt-bindings/gpio/gpio.h>
  76. +
  77. +/ {
  78. + model = "Marvell Armada 385 Access Point Development Board";
  79. + compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
  80. +
  81. + chosen {
  82. + bootargs = "console=ttyS0,115200";
  83. + stdout-path = &uart1;
  84. + };
  85. +
  86. + memory {
  87. + device_type = "memory";
  88. + reg = <0x00000000 0x80000000>; /* 2GB */
  89. + };
  90. +
  91. + soc {
  92. + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  93. + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  94. +
  95. + internal-regs {
  96. + spi1: spi@10680 {
  97. + pinctrl-names = "default";
  98. + pinctrl-0 = <&spi1_pins>;
  99. + status = "okay";
  100. +
  101. + spi-flash@0 {
  102. + #address-cells = <1>;
  103. + #size-cells = <1>;
  104. + compatible = "st,m25p128";
  105. + reg = <0>; /* Chip select 0 */
  106. + spi-max-frequency = <54000000>;
  107. + };
  108. + };
  109. +
  110. + i2c0: i2c@11000 {
  111. + pinctrl-names = "default";
  112. + pinctrl-0 = <&i2c0_pins>;
  113. + status = "okay";
  114. +
  115. + /*
  116. + * This bus is wired to two EEPROM
  117. + * sockets, one of which holding the
  118. + * board ID used by the bootloader.
  119. + * Erasing this EEPROM's content will
  120. + * brick the board.
  121. + * Use this bus with caution.
  122. + */
  123. + };
  124. +
  125. + mdio@72004 {
  126. + pinctrl-names = "default";
  127. + pinctrl-0 = <&mdio_pins>;
  128. +
  129. + phy0: ethernet-phy@1 {
  130. + reg = <1>;
  131. + };
  132. +
  133. + phy1: ethernet-phy@4 {
  134. + reg = <4>;
  135. + };
  136. +
  137. + phy2: ethernet-phy@6 {
  138. + reg = <6>;
  139. + };
  140. + };
  141. +
  142. + /* UART0 is exposed through the JP8 connector */
  143. + uart0: serial@12000 {
  144. + pinctrl-names = "default";
  145. + pinctrl-0 = <&uart0_pins>;
  146. + status = "okay";
  147. + };
  148. +
  149. + /*
  150. + * UART1 is exposed through a FTDI chip
  151. + * wired to the mini-USB connector
  152. + */
  153. + uart1: serial@12100 {
  154. + pinctrl-names = "default";
  155. + pinctrl-0 = <&uart1_pins>;
  156. + status = "okay";
  157. + };
  158. +
  159. + ethernet@30000 {
  160. + status = "okay";
  161. + phy = <&phy2>;
  162. + phy-mode = "sgmii";
  163. + };
  164. +
  165. + ethernet@34000 {
  166. + status = "okay";
  167. + phy = <&phy1>;
  168. + phy-mode = "sgmii";
  169. + };
  170. +
  171. + ethernet@70000 {
  172. + pinctrl-names = "default";
  173. +
  174. + /*
  175. + * The Reference Clock 0 is used to
  176. + * provide a clock to the PHY
  177. + */
  178. + pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
  179. + status = "okay";
  180. + phy = <&phy0>;
  181. + phy-mode = "rgmii-id";
  182. + };
  183. + };
  184. +
  185. + pcie-controller {
  186. + status = "okay";
  187. +
  188. + /*
  189. + * The three PCIe units are accessible through
  190. + * standard mini-PCIe slots on the board.
  191. + */
  192. + pcie@1,0 {
  193. + /* Port 0, Lane 0 */
  194. + status = "okay";
  195. + };
  196. +
  197. + pcie@2,0 {
  198. + /* Port 1, Lane 0 */
  199. + status = "okay";
  200. + };
  201. +
  202. + pcie@3,0 {
  203. + /* Port 2, Lane 0 */
  204. + status = "okay";
  205. + };
  206. + };
  207. + };
  208. +};