WL-351.dts 2.0 KB

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  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. / {
  4. compatible = "WL-351", "ralink,rt3052-soc";
  5. model = "Sitecom WL-351 v1 002";
  6. cfi@1f000000 {
  7. compatible = "cfi-flash";
  8. reg = <0x1f000000 0x800000>;
  9. bank-width = <2>;
  10. device-width = <2>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. partition@0 {
  14. label = "u-boot";
  15. reg = <0x0 0x30000>;
  16. read-only;
  17. };
  18. partition@30000 {
  19. label = "u-boot-env";
  20. reg = <0x30000 0x10000>;
  21. read-only;
  22. };
  23. factory: partition@40000 {
  24. label = "factory";
  25. reg = <0x40000 0x10000>;
  26. read-only;
  27. };
  28. partition@50000 {
  29. label = "firmware";
  30. reg = <0x50000 0x3b0000>;
  31. };
  32. };
  33. gpio-leds {
  34. compatible = "gpio-leds";
  35. power {
  36. label = "wl-351:amber:power";
  37. gpios = <&gpio0 8 1>;
  38. };
  39. unpopulated {
  40. label = "wl-351:amber:unpopulated";
  41. gpios = <&gpio0 12 1>;
  42. };
  43. unpopulated2 {
  44. label = "wl-351:blue:unpopulated";
  45. gpios = <&gpio0 13 1>;
  46. };
  47. };
  48. gpio-keys-polled {
  49. compatible = "gpio-keys-polled";
  50. #address-cells = <1>;
  51. #size-cells = <0>;
  52. poll-interval = <20>;
  53. reset {
  54. label = "reset";
  55. gpios = <&gpio0 10 1>;
  56. linux,code = <0x198>;
  57. };
  58. wps {
  59. label = "wps";
  60. gpios = <&gpio0 0 1>;
  61. linux,code = <0x211>;
  62. };
  63. };
  64. rtl8366rb {
  65. compatible = "rtl8366rb";
  66. gpio-sda = <&gpio0 1 0>;
  67. gpio-sck = <&gpio0 2 0>;
  68. };
  69. };
  70. &pinctrl {
  71. state_default: pinctrl0 {
  72. gpio {
  73. ralink,group = "spi", "i2c", "jtag", "mdio", "uartf";
  74. ralink,function = "gpio";
  75. };
  76. rgmii {
  77. ralink,group = "rgmii";
  78. ralink,function = "rgmii";
  79. };
  80. };
  81. };
  82. &ethernet {
  83. mtd-mac-address = <&factory 0x4>;
  84. };
  85. &esw {
  86. ralink,rgmii = <1>;
  87. mediatek,portmap = <0x3f>;
  88. ralink,fct2 = <0x0002500c>;
  89. /*
  90. * ext phy base addr 31, rx/tx clock skew 0,
  91. * turbo mii off, rgmi 3.3v off, port 5 polling off
  92. * port5: enabled, gige, full-duplex, rx/tx-flow-control
  93. * port6: enabled, gige, full-duplex, rx/tx-flow-control
  94. */
  95. ralink,fpa2 = <0x1f003fff>;
  96. };
  97. &wmac {
  98. ralink,mtd-eeprom = <&factory 0>;
  99. };
  100. &otg {
  101. status = "okay";
  102. };