NA930.dts 2.3 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  5. model = "Sercomm NA930";
  6. chosen {
  7. bootargs = "console=ttyS1,57600";
  8. };
  9. nand {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "mtk,mt7620-nand";
  13. partition@0 {
  14. label = "u-boot";
  15. reg = <0x0 0x20000>;
  16. read-only;
  17. };
  18. partition@200000 {
  19. label = "factory";
  20. reg = <0x200000 0x40000>;
  21. read-only;
  22. };
  23. partition@240000 {
  24. label = "Config";
  25. reg = <0x240000 0x400000>;
  26. read-only;
  27. };
  28. partition@640000 {
  29. label = "firmware";
  30. reg = <0x640000 0x1400000>;
  31. };
  32. };
  33. gpio-keys-polled {
  34. compatible = "gpio-keys-polled";
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. poll-interval = <20>;
  38. reset {
  39. label = "reset";
  40. gpios = <&gpio0 11 1>;
  41. linux,code = <0x198>;
  42. };
  43. zwave {
  44. label = "zwave";
  45. gpios = <&gpio0 12 1>;
  46. linux,code = <0x100>;
  47. };
  48. wps {
  49. label = "wps";
  50. gpios = <&gpio0 14 1>;
  51. linux,code = <0x211>;
  52. };
  53. };
  54. gpio-leds {
  55. compatible = "gpio-leds";
  56. zwave {
  57. label = "na930:blue:zwave";
  58. gpios = <&gpio2 0 1>;
  59. };
  60. status {
  61. label = "na930:blue:status";
  62. gpios = <&gpio2 26 1>;
  63. };
  64. service {
  65. label = "na930:blue:service";
  66. gpios = <&gpio2 28 1>;
  67. };
  68. power {
  69. label = "na930:blue:power";
  70. gpios = <&gpio2 29 1>;
  71. };
  72. };
  73. gpio_export {
  74. compatible = "gpio-export";
  75. #size-cells = <0>;
  76. telit {
  77. gpio-export,name = "telit";
  78. gpio-export,output = <1>;
  79. gpios = <&gpio0 13 0>;
  80. };
  81. };
  82. };
  83. &pinctrl {
  84. state_default: pinctrl0 {
  85. gpio {
  86. ralink,group = "i2c", "rgmii2", "spi", "ephy";
  87. ralink,function = "gpio";
  88. };
  89. uartf_gpio {
  90. ralink,group = "uartf";
  91. ralink,function = "gpio uartf";
  92. };
  93. };
  94. };
  95. &uart {
  96. status = "okay";
  97. };
  98. &gpio1 {
  99. status = "okay";
  100. };
  101. &gpio2 {
  102. status = "okay";
  103. };
  104. &ethernet {
  105. status = "okay";
  106. pinctrl-names = "default";
  107. pinctrl-0 = <&rgmii1_pins &mdio_pins>;
  108. mediatek,portmap = "llllw";
  109. port@4 {
  110. status = "okay";
  111. phy-handle = <&phy4>;
  112. phy-mode = "rgmii";
  113. };
  114. port@5 {
  115. status = "okay";
  116. phy-handle = <&phy5>;
  117. phy-mode = "rgmii";
  118. };
  119. mdio-bus {
  120. status = "okay";
  121. phy4: ethernet-phy@4 {
  122. reg = <4>;
  123. phy-mode = "rgmii";
  124. };
  125. phy5: ethernet-phy@5 {
  126. reg = <5>;
  127. phy-mode = "rgmii";
  128. };
  129. };
  130. };
  131. &gsw {
  132. mediatek,port4 = "gmac";
  133. };
  134. &ehci {
  135. status = "okay";
  136. };
  137. &ohci {
  138. status = "okay";
  139. };