MZK-750DHP.dts 1.8 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-soc";
  5. model = "Planex MZK-750DHP";
  6. gpio-leds {
  7. compatible = "gpio-leds";
  8. wps {
  9. label = "mzk-750dhp:green:wps";
  10. gpios = <&gpio2 15 1>;
  11. };
  12. power {
  13. label = "mzk-750dhp:green:power";
  14. gpios = <&gpio1 15 1>;
  15. };
  16. wlan5g {
  17. label = "mzk-750dhp:green:wlan5g";
  18. gpios = <&gpio1 14 1>;
  19. };
  20. };
  21. gpio-keys-polled {
  22. compatible = "gpio-keys-polled";
  23. #address-cells = <1>;
  24. #size-cells = <0>;
  25. poll-interval = <20>;
  26. s1 {
  27. label = "reset";
  28. gpios = <&gpio0 1 1>;
  29. linux,code = <0x198>;
  30. };
  31. s2 {
  32. label = "wps";
  33. gpios = <&gpio2 19 1>;
  34. linux,code = <0x211>;
  35. };
  36. };
  37. };
  38. &gpio1 {
  39. status = "okay";
  40. };
  41. &gpio2 {
  42. status = "okay";
  43. };
  44. &spi0 {
  45. status = "okay";
  46. m25p80@0 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. compatible = "jedec,spi-nor";
  50. reg = <0>;
  51. linux,modalias = "m25p80", "mx25l6405d";
  52. spi-max-frequency = <10000000>;
  53. partition@0 {
  54. label = "u-boot";
  55. reg = <0x0 0x30000>;
  56. read-only;
  57. };
  58. partition@30000 {
  59. label = "u-boot-env";
  60. reg = <0x30000 0x10000>;
  61. read-only;
  62. };
  63. factory: partition@40000 {
  64. label = "factory";
  65. reg = <0x40000 0x10000>;
  66. read-only;
  67. };
  68. partition@50000 {
  69. label = "firmware";
  70. reg = <0x50000 0x7b0000>;
  71. };
  72. };
  73. };
  74. &pinctrl {
  75. state_default: pinctrl0 {
  76. gpio {
  77. ralink,group = "i2c", "spi refclk", "rgmii1", "nd_sd";
  78. ralink,function = "gpio";
  79. };
  80. };
  81. };
  82. &ethernet {
  83. pinctrl-names = "default";
  84. pinctrl-0 = <&ephy_pins>;
  85. mtd-mac-address = <&factory 0x4>;
  86. mediatek,portmap = "llllw";
  87. };
  88. &gsw {
  89. mediatek,port4 = "ephy";
  90. };
  91. &wmac {
  92. ralink,mtd-eeprom = <&factory 0>;
  93. };
  94. &pcie {
  95. status = "okay";
  96. pcie-bridge {
  97. mt76@0,0 {
  98. reg = <0x0000 0 0 0 0>;
  99. device_type = "pci";
  100. mediatek,mtd-eeprom = <&factory 0x8000>;
  101. mediatek,2ghz = <0>;
  102. };
  103. };
  104. };