JHR-N825R.dts 1.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081
  1. /dts-v1/;
  2. #include "rt3050.dtsi"
  3. / {
  4. compatible = "JHR-N825R", "ralink,rt3052-soc";
  5. model = "JCG JHR-N825R";
  6. cfi@1f000000 {
  7. compatible = "cfi-flash";
  8. reg = <0x1f000000 0x800000>;
  9. bank-width = <2>;
  10. device-width = <2>;
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. partition@0 {
  14. label = "u-boot";
  15. reg = <0x0 0x30000>;
  16. read-only;
  17. };
  18. partition@30000 {
  19. label = "u-boot-env";
  20. reg = <0x30000 0x10000>;
  21. read-only;
  22. };
  23. factory: partition@40000 {
  24. label = "factory";
  25. reg = <0x40000 0x10000>;
  26. read-only;
  27. };
  28. partition@50000 {
  29. label = "firmware";
  30. reg = <0x50000 0x3b0000>;
  31. };
  32. };
  33. gpio-leds {
  34. compatible = "gpio-leds";
  35. system {
  36. label = "jhr-n825r:red:power";
  37. gpios = <&gpio0 9 1>;
  38. };
  39. };
  40. gpio-keys-polled {
  41. compatible = "gpio-keys-polled";
  42. #address-cells = <1>;
  43. #size-cells = <0>;
  44. poll-interval = <20>;
  45. reset_wps {
  46. label = "reset_wps";
  47. gpios = <&gpio0 10 1>;
  48. linux,code = <0x198>;
  49. };
  50. };
  51. };
  52. &pinctrl {
  53. state_default: pinctrl0 {
  54. gpio {
  55. ralink,group = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  56. ralink,function = "gpio";
  57. };
  58. };
  59. };
  60. &ethernet {
  61. mtd-mac-address = <&factory 0x2e>;
  62. };
  63. &esw {
  64. mediatek,portmap = <0x3e>;
  65. };
  66. &wmac {
  67. ralink,mtd-eeprom = <&factory 0>;
  68. };