MT7620a_V22SG.dts 1.6 KB

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  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  5. model = "Ralink MT7620a V22SG High Power evaluation board";
  6. gpio-keys-polled {
  7. compatible = "gpio-keys-polled";
  8. #address-cells = <1>;
  9. #size-cells = <0>;
  10. poll-interval = <20>;
  11. reset {
  12. label = "reset";
  13. gpios = <&gpio0 1 1>;
  14. linux,code = <0x198>;
  15. };
  16. aoss {
  17. label = "aoss";
  18. gpios = <&gpio0 2 1>;
  19. linux,code = <0x211>;
  20. };
  21. };
  22. nand {
  23. #address-cells = <1>;
  24. #size-cells = <1>;
  25. compatible = "mtk,mt7620-nand";
  26. partition@0 {
  27. label = "u-boot";
  28. reg = <0x0 0x40000>;
  29. read-only;
  30. };
  31. partition@40000 {
  32. label = "u-boot-env";
  33. reg = <0x40000 0x20000>;
  34. read-only;
  35. };
  36. factory: partition@60000 {
  37. label = "factory";
  38. reg = <0x60000 0x20000>;
  39. read-only;
  40. };
  41. partition@80000 {
  42. label = "firmware";
  43. reg = <0x80000 0x7f80000>;
  44. };
  45. };
  46. };
  47. &pinctrl {
  48. state_default: pinctrl0 {
  49. gpio {
  50. ralink,group = "i2c", "uartf", "spi";
  51. ralink,function = "gpio";
  52. };
  53. };
  54. };
  55. &ethernet {
  56. status = "okay";
  57. pinctrl-names = "default";
  58. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  59. mediatek,portmap = "llllw";
  60. port@4 {
  61. status = "okay";
  62. phy-handle = <&phy4>;
  63. phy-mode = "rgmii";
  64. };
  65. port@5 {
  66. status = "okay";
  67. phy-handle = <&phy5>;
  68. phy-mode = "rgmii";
  69. };
  70. mdio-bus {
  71. status = "okay";
  72. phy4: ethernet-phy@4 {
  73. reg = <4>;
  74. phy-mode = "rgmii";
  75. };
  76. phy5: ethernet-phy@5 {
  77. reg = <5>;
  78. phy-mode = "rgmii";
  79. };
  80. };
  81. };
  82. &gsw {
  83. mediatek,port4 = "gmac";
  84. };
  85. &pcie {
  86. status = "okay";
  87. };
  88. &ehci {
  89. status = "okay";
  90. };
  91. &ohci {
  92. status = "okay";
  93. };