MT7620a_MT7530.dts 1.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117
  1. /dts-v1/;
  2. #include "mt7620a.dtsi"
  3. / {
  4. compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
  5. model = "Ralink MT7620a + MT7530 evaluation board";
  6. };
  7. &spi0 {
  8. status = "okay";
  9. m25p80@0 {
  10. #address-cells = <1>;
  11. #size-cells = <1>;
  12. compatible = "jedec,spi-nor";
  13. reg = <0>;
  14. linux,modalias = "m25p80", "s25fl064k";
  15. spi-max-frequency = <10000000>;
  16. partition@0 {
  17. label = "u-boot";
  18. reg = <0x0 0x30000>;
  19. read-only;
  20. };
  21. partition@30000 {
  22. label = "u-boot-env";
  23. reg = <0x30000 0x10000>;
  24. read-only;
  25. };
  26. factory: partition@40000 {
  27. label = "factory";
  28. reg = <0x40000 0x10000>;
  29. read-only;
  30. };
  31. partition@50000 {
  32. label = "firmware";
  33. reg = <0x50000 0x7b0000>;
  34. };
  35. };
  36. };
  37. &pinctrl {
  38. state_default: pinctrl0 {
  39. gpio {
  40. ralink,group = "i2c", "uartf";
  41. ralink,function = "gpio";
  42. };
  43. };
  44. };
  45. &ethernet {
  46. status = "okay";
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
  49. mediatek,portmap = "llllw";
  50. port@5 {
  51. status = "okay";
  52. mediatek,fixed-link = <1000 1 1 1>;
  53. phy-mode = "rgmii";
  54. };
  55. mdio-bus {
  56. status = "okay";
  57. phy0: ethernet-phy@0 {
  58. reg = <0>;
  59. phy-mode = "rgmii";
  60. };
  61. phy1: ethernet-phy@1 {
  62. reg = <1>;
  63. phy-mode = "rgmii";
  64. };
  65. phy2: ethernet-phy@2 {
  66. reg = <2>;
  67. phy-mode = "rgmii";
  68. };
  69. phy3: ethernet-phy@3 {
  70. reg = <3>;
  71. phy-mode = "rgmii";
  72. };
  73. phy4: ethernet-phy@4 {
  74. reg = <4>;
  75. phy-mode = "rgmii";
  76. };
  77. phy1f: ethernet-phy@1f {
  78. reg = <0x1f>;
  79. phy-mode = "rgmii";
  80. };
  81. };
  82. };
  83. &gsw {
  84. mediatek,port4 = "gmac";
  85. mediatek,mt7530 = <1>;
  86. };
  87. &pcie {
  88. status = "okay";
  89. };
  90. &ehci {
  91. status = "okay";
  92. };
  93. &ohci {
  94. status = "okay";
  95. };