driver-avalon7.c 74 KB

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  1. /*
  2. * Copyright 2016 Mikeqin <Fengling.Qin@gmail.com>
  3. * Copyright 2016 Con Kolivas <kernel@kolivas.org>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License as published by the Free
  7. * Software Foundation; either version 3 of the License, or (at your option)
  8. * any later version. See COPYING for more details.
  9. */
  10. #include <math.h>
  11. #include "config.h"
  12. #include "miner.h"
  13. #include "driver-avalon7.h"
  14. #include "crc.h"
  15. #include "sha2.h"
  16. #include "hexdump.c"
  17. #define get_fan_pwm(v) (AVA7_PWM_MAX - (v) * AVA7_PWM_MAX / 100)
  18. int opt_avalon7_temp_target = AVA7_DEFAULT_TEMP_TARGET;
  19. int opt_avalon7_fan_min = AVA7_DEFAULT_FAN_MIN;
  20. int opt_avalon7_fan_max = AVA7_DEFAULT_FAN_MAX;
  21. int opt_avalon7_voltage = AVA7_INVALID_VOLTAGE;
  22. int opt_avalon7_voltage_offset = AVA7_DEFAULT_VOLTAGE_OFFSET;
  23. int opt_avalon7_freq[AVA7_DEFAULT_PLL_CNT] = {AVA7_DEFAULT_FREQUENCY_0,
  24. AVA7_DEFAULT_FREQUENCY_1,
  25. AVA7_DEFAULT_FREQUENCY_2,
  26. AVA7_DEFAULT_FREQUENCY_3,
  27. AVA7_DEFAULT_FREQUENCY_4,
  28. AVA7_DEFAULT_FREQUENCY_5};
  29. int opt_avalon7_freq_sel = AVA7_DEFAULT_FREQUENCY_SEL;
  30. int opt_avalon7_polling_delay = AVA7_DEFAULT_POLLING_DELAY;
  31. int opt_avalon7_aucspeed = AVA7_AUC_SPEED;
  32. int opt_avalon7_aucxdelay = AVA7_AUC_XDELAY;
  33. int opt_avalon7_smart_speed = AVA7_DEFAULT_SMART_SPEED;
  34. /*
  35. * smart speed have 2 modes
  36. * 1. auto speed by A3212 chips
  37. * 2. option 1 + adjust by average frequency
  38. */
  39. bool opt_avalon7_iic_detect = AVA7_DEFAULT_IIC_DETECT;
  40. uint32_t opt_avalon7_th_pass = AVA7_DEFAULT_TH_PASS;
  41. uint32_t opt_avalon7_th_fail = AVA7_DEFAULT_TH_FAIL;
  42. uint32_t opt_avalon7_th_init = AVA7_DEFAULT_TH_INIT;
  43. uint32_t opt_avalon7_th_ms = AVA7_DEFAULT_TH_MS;
  44. uint32_t opt_avalon7_th_timeout = AVA7_DEFAULT_TH_TIMEOUT;
  45. uint32_t opt_avalon7_nonce_mask = AVA7_DEFAULT_NONCE_MASK;
  46. bool opt_avalon7_asic_debug = true;
  47. uint32_t cpm_table[] =
  48. {
  49. 0x0173f813,
  50. 0x0175f813,
  51. 0x0163f813,
  52. 0x0164f813,
  53. 0x0165f813,
  54. 0x0166f813,
  55. 0x0153f813,
  56. 0x01547813,
  57. 0x0154f813,
  58. 0x01557813,
  59. 0x0155f813,
  60. 0x01567813,
  61. 0x0156f813,
  62. 0x01577813,
  63. 0x0143f813,
  64. 0x01443813,
  65. 0x01447813,
  66. 0x0144b813,
  67. 0x0144f813,
  68. 0x01453813,
  69. 0x01457813,
  70. 0x0145b813,
  71. 0x0145f813,
  72. 0x01463813,
  73. 0x01467813,
  74. 0x0146b813,
  75. 0x0146f813,
  76. 0x01473813,
  77. 0x01477813,
  78. 0x0147b813,
  79. 0x0133f813,
  80. 0x01341813,
  81. 0x01343813,
  82. 0x01345813,
  83. 0x01347813,
  84. 0x01349813,
  85. 0x0134b813,
  86. 0x0134d813,
  87. 0x0134f813,
  88. 0x01351813,
  89. 0x01353813,
  90. 0x01355813,
  91. 0x01357813,
  92. 0x01359813,
  93. 0x0135b813,
  94. 0x0135d813,
  95. 0x0135f813,
  96. 0x01361813,
  97. 0x01363813,
  98. 0x01365813,
  99. 0x01367813,
  100. 0x01369813,
  101. 0x0136b813,
  102. 0x0136d813,
  103. 0x0136f813,
  104. 0x01371813,
  105. 0x01373813,
  106. 0x01375813,
  107. 0x01377813,
  108. 0x01379813,
  109. 0x0137b813,
  110. 0x0123e813,
  111. 0x0123f813,
  112. 0x01240813,
  113. 0x01241813,
  114. 0x01242813,
  115. 0x01243813,
  116. 0x01244813,
  117. 0x01245813,
  118. 0x01246813,
  119. 0x01247813,
  120. 0x01248813,
  121. 0x01249813,
  122. 0x0124a813,
  123. 0x0124b813,
  124. 0x0124c813,
  125. 0x0124d813,
  126. 0x0124e813,
  127. 0x0124f813,
  128. 0x01250813,
  129. 0x01251813,
  130. 0x01252813,
  131. 0x01253813,
  132. 0x01254813,
  133. 0x01255813,
  134. 0x01256813,
  135. 0x01257813,
  136. 0x01258813,
  137. 0x01259813,
  138. 0x0125a813,
  139. 0x0125b813,
  140. 0x0125c813,
  141. 0x0125d813,
  142. 0x0125e813,
  143. 0x0125f813,
  144. 0x01260813,
  145. 0x01261813,
  146. 0x01262813,
  147. 0x01263813,
  148. 0x01264813,
  149. 0x01265813,
  150. 0x01266813,
  151. 0x01267813,
  152. 0x01268813,
  153. 0x01269813,
  154. 0x0126a813,
  155. 0x0126b813,
  156. 0x0126c813,
  157. 0x0126d813,
  158. 0x0126e813,
  159. 0x0126f813,
  160. 0x01270813,
  161. 0x01271813,
  162. 0x01272813,
  163. 0x01273813,
  164. 0x01274813,
  165. };
  166. struct avalon7_dev_description avalon7_dev_table[] = {
  167. {
  168. "711",
  169. 711,
  170. 4,
  171. 18,
  172. AVA7_MM711_VIN_ADC_RATIO,
  173. AVA7_MM711_VOUT_ADC_RATIO,
  174. 4981
  175. },
  176. {
  177. "721",
  178. 721,
  179. 4,
  180. 18,
  181. AVA7_MM721_VIN_ADC_RATIO,
  182. AVA7_MM721_VOUT_ADC_RATIO,
  183. 4981
  184. },
  185. {
  186. "741",
  187. 741,
  188. 4,
  189. 22,
  190. AVA7_MM741_VIN_ADC_RATIO,
  191. AVA7_MM741_VOUT_ADC_RATIO,
  192. 4825,
  193. },
  194. {
  195. "761",
  196. 761,
  197. 4,
  198. 26,
  199. AVA7_MM761_VIN_ADC_RATIO,
  200. AVA7_MM761_VOUT_ADC_RATIO,
  201. 4825,
  202. }
  203. };
  204. static uint32_t api_get_cpm(uint32_t freq)
  205. {
  206. return cpm_table[freq / 12 - 2];
  207. }
  208. static uint32_t encode_voltage(uint32_t volt)
  209. {
  210. if (volt > AVA7_DEFAULT_VOLTAGE_MAX)
  211. volt = AVA7_DEFAULT_VOLTAGE_MAX;
  212. if (volt < AVA7_DEFAULT_VOLTAGE_MIN)
  213. volt = AVA7_DEFAULT_VOLTAGE_MIN;
  214. return 0x8000 | ((volt - AVA7_DEFAULT_VOLTAGE_MIN) / AVA7_DEFAULT_VOLTAGE_STEP);
  215. }
  216. static uint32_t convert_voltage_level(uint32_t level)
  217. {
  218. if (level > AVA7_DEFAULT_VOLTAGE_LEVEL_MAX)
  219. level = AVA7_DEFAULT_VOLTAGE_LEVEL_MAX;
  220. return AVA7_DEFAULT_VOLTAGE_MIN + level * AVA7_DEFAULT_VOLTAGE_STEP;
  221. }
  222. static uint32_t decode_voltage(struct avalon7_info *info, int modular_id, uint32_t volt)
  223. {
  224. return (volt * info->vout_adc_ratio[modular_id] / info->asic_count[modular_id] / 100);
  225. }
  226. static uint16_t decode_vin(struct avalon7_info *info, int modular_id, uint16_t volt)
  227. {
  228. return (volt * info->vin_adc_ratio[modular_id] / 1000);
  229. }
  230. static double decode_pvt_temp(uint16_t pvt_code)
  231. {
  232. double a4 = -1.1876E-11;
  233. double a3 = 6.6675E-08;
  234. double a2 = -1.7724E-04;
  235. double a1 = 3.3691E-01;
  236. double a0 = -6.0605E+01;
  237. return a4 * pow(pvt_code, 4) + a3 * pow(pvt_code, 3) + a2 * pow(pvt_code, 2) + a1 * pow(pvt_code, 1) + a0;
  238. }
  239. #define SERIESRESISTOR 10000
  240. #define THERMISTORNOMINAL 10000
  241. #define BCOEFFICIENT 3500
  242. #define TEMPERATURENOMINAL 25
  243. float decode_auc_temp(int value)
  244. {
  245. float ret, resistance;
  246. if (!((value > 0) && (value < 33000)))
  247. return -273;
  248. resistance = (3.3 * 10000 / value) - 1;
  249. resistance = SERIESRESISTOR / resistance;
  250. ret = resistance / THERMISTORNOMINAL;
  251. ret = logf(ret);
  252. ret /= BCOEFFICIENT;
  253. ret += 1.0 / (TEMPERATURENOMINAL + 273.15);
  254. ret = 1.0 / ret;
  255. ret -= 273.15;
  256. return ret;
  257. }
  258. #define UNPACK32(x, str) \
  259. { \
  260. *((str) + 3) = (uint8_t) ((x) ); \
  261. *((str) + 2) = (uint8_t) ((x) >> 8); \
  262. *((str) + 1) = (uint8_t) ((x) >> 16); \
  263. *((str) + 0) = (uint8_t) ((x) >> 24); \
  264. }
  265. static inline void sha256_prehash(const unsigned char *message, unsigned int len, unsigned char *digest)
  266. {
  267. int i;
  268. sha256_ctx ctx;
  269. sha256_init(&ctx);
  270. sha256_update(&ctx, message, len);
  271. for (i = 0; i < 8; i++)
  272. UNPACK32(ctx.h[i], &digest[i << 2]);
  273. }
  274. char *set_avalon7_fan(char *arg)
  275. {
  276. int val1, val2, ret;
  277. ret = sscanf(arg, "%d-%d", &val1, &val2);
  278. if (ret < 1)
  279. return "No value passed to avalon7-fan";
  280. if (ret == 1)
  281. val2 = val1;
  282. if (val1 < 0 || val1 > 100 || val2 < 0 || val2 > 100 || val2 < val1)
  283. return "Invalid value passed to avalon7-fan";
  284. opt_avalon7_fan_min = val1;
  285. opt_avalon7_fan_max = val2;
  286. return NULL;
  287. }
  288. char *set_avalon7_freq(char *arg)
  289. {
  290. int val[AVA7_DEFAULT_PLL_CNT];
  291. char *colon, *data;
  292. int i;
  293. if (!(*arg))
  294. return NULL;
  295. data = arg;
  296. memset(val, 0, sizeof(val));
  297. for (i = 0; i < AVA7_DEFAULT_PLL_CNT; i++) {
  298. colon = strchr(data, ':');
  299. if (colon)
  300. *(colon++) = '\0';
  301. else {
  302. /* last value */
  303. if (*data) {
  304. val[i] = atoi(data);
  305. if (val[i] < AVA7_DEFAULT_FREQUENCY_MIN || val[i] > AVA7_DEFAULT_FREQUENCY_MAX)
  306. return "Invalid value passed to avalon7-freq";
  307. }
  308. break;
  309. }
  310. if (*data) {
  311. val[i] = atoi(data);
  312. if (val[i] < AVA7_DEFAULT_FREQUENCY_MIN || val[i] > AVA7_DEFAULT_FREQUENCY_MAX)
  313. return "Invalid value passed to avalon7-freq";
  314. }
  315. data = colon;
  316. }
  317. for (i = 0; i < AVA7_DEFAULT_PLL_CNT; i++) {
  318. if (!val[i] && i)
  319. val[i] = val[i - 1];
  320. opt_avalon7_freq[i] = val[i];
  321. }
  322. return NULL;
  323. }
  324. char *set_avalon7_voltage(char *arg)
  325. {
  326. int val, ret;
  327. ret = sscanf(arg, "%d", &val);
  328. if (ret < 1)
  329. return "No value passed to avalon7-voltage";
  330. if (val < AVA7_DEFAULT_VOLTAGE_MIN || val > AVA7_DEFAULT_VOLTAGE_MAX)
  331. return "Invalid value passed to avalon7-voltage";
  332. opt_avalon7_voltage = val;
  333. return NULL;
  334. }
  335. char *set_avalon7_voltage_level(char *arg)
  336. {
  337. int val, ret;
  338. ret = sscanf(arg, "%d", &val);
  339. if (ret < 1)
  340. return "No value passed to avalon7-voltage-level";
  341. if (val < AVA7_DEFAULT_VOLTAGE_LEVEL_MIN || val > AVA7_DEFAULT_VOLTAGE_LEVEL_MAX)
  342. return "Invalid value passed to avalon7-voltage-level";
  343. opt_avalon7_voltage = convert_voltage_level(val);
  344. return NULL;
  345. }
  346. char *set_avalon7_voltage_offset(char *arg)
  347. {
  348. int val, ret;
  349. ret = sscanf(arg, "%d", &val);
  350. if (ret < 1)
  351. return "No value passed to avalon7-voltage-offset";
  352. if (val < AVA7_DEFAULT_VOLTAGE_OFFSET_MIN || val > AVA7_DEFAULT_VOLTAGE_OFFSET_MAX)
  353. return "Invalid value passed to avalon7-voltage-offset";
  354. opt_avalon7_voltage_offset = val;
  355. return NULL;
  356. }
  357. static int avalon7_init_pkg(struct avalon7_pkg *pkg, uint8_t type, uint8_t idx, uint8_t cnt)
  358. {
  359. unsigned short crc;
  360. pkg->head[0] = AVA7_H1;
  361. pkg->head[1] = AVA7_H2;
  362. pkg->type = type;
  363. pkg->opt = 0;
  364. pkg->idx = idx;
  365. pkg->cnt = cnt;
  366. crc = crc16(pkg->data, AVA7_P_DATA_LEN);
  367. pkg->crc[0] = (crc & 0xff00) >> 8;
  368. pkg->crc[1] = crc & 0xff;
  369. return 0;
  370. }
  371. static int job_idcmp(uint8_t *job_id, char *pool_job_id)
  372. {
  373. int job_id_len;
  374. unsigned short crc, crc_expect;
  375. if (!pool_job_id)
  376. return 1;
  377. job_id_len = strlen(pool_job_id);
  378. crc_expect = crc16((unsigned char *)pool_job_id, job_id_len);
  379. crc = job_id[0] << 8 | job_id[1];
  380. if (crc_expect == crc)
  381. return 0;
  382. applog(LOG_DEBUG, "avalon7: job_id doesn't match! [%04x:%04x (%s)]",
  383. crc, crc_expect, pool_job_id);
  384. return 1;
  385. }
  386. static inline int get_temp_max(struct avalon7_info *info, int addr)
  387. {
  388. int i;
  389. int max = -273;
  390. for (i = 0; i < info->miner_count[addr]; i++) {
  391. if (info->temp[addr][i][3] > max)
  392. max = info->temp[addr][i][3];
  393. }
  394. if (max < info->temp_mm[addr])
  395. max = info->temp_mm[addr];
  396. return max;
  397. }
  398. /* Use a PID-like feedback mechanism for optimal temperature and fan speed */
  399. static inline uint32_t adjust_fan(struct avalon7_info *info, int id)
  400. {
  401. int t, tdiff, delta;
  402. uint32_t pwm;
  403. time_t now_t;
  404. now_t = time(NULL);
  405. t = get_temp_max(info, id);
  406. tdiff = t - info->temp_last_max[id];
  407. if (!tdiff && now_t < info->last_temp_time[id] + AVA7_DEFAULT_FAN_INTERVAL)
  408. goto out;
  409. info->last_temp_time[id] = now_t;
  410. delta = t - info->temp_target[id];
  411. /* Check for init value and ignore it */
  412. if (unlikely(info->temp_last_max[id] == -273))
  413. tdiff = 0;
  414. info->temp_last_max[id] = t;
  415. if (t >= info->temp_overheat[id]) {
  416. /* Hit the overheat temperature limit */
  417. if (info->fan_pct[id] < opt_avalon7_fan_max) {
  418. applog(LOG_WARNING, "Overheat detected on AV7-%d, increasing fan to max", id);
  419. info->fan_pct[id] = opt_avalon7_fan_max;
  420. }
  421. } else if (delta > 0) {
  422. /* Over target temperature. */
  423. /* Is the temp already coming down */
  424. if (tdiff < 0)
  425. goto out;
  426. /* Adjust fanspeed by temperature over and any further rise */
  427. info->fan_pct[id] += delta + tdiff;
  428. } else {
  429. /* Below target temperature */
  430. int diff = tdiff;
  431. if (tdiff > 0) {
  432. int divisor = -delta / AVA7_DEFAULT_TEMP_HYSTERESIS + 1;
  433. /* Adjust fanspeed by temperature change proportional to
  434. * diff from optimal. */
  435. diff /= divisor;
  436. } else {
  437. /* Is the temp below optimal and unchanging, gently lower speed */
  438. if (t < info->temp_target[id] - AVA7_DEFAULT_TEMP_HYSTERESIS && !tdiff)
  439. diff -= 1;
  440. }
  441. info->fan_pct[id] += diff;
  442. }
  443. if (info->fan_pct[id] > opt_avalon7_fan_max)
  444. info->fan_pct[id] = opt_avalon7_fan_max;
  445. else if (info->fan_pct[id] < opt_avalon7_fan_min)
  446. info->fan_pct[id] = opt_avalon7_fan_min;
  447. out:
  448. pwm = get_fan_pwm(info->fan_pct[id]);
  449. if (info->cutoff[id])
  450. pwm = get_fan_pwm(opt_avalon7_fan_max);
  451. applog(LOG_DEBUG, "[%d], Adjust_fan: %dC-%d%%(%03x)", id, t, info->fan_pct[id], pwm);
  452. return pwm;
  453. }
  454. static int decode_pkg(struct cgpu_info *avalon7, struct avalon7_ret *ar, int modular_id)
  455. {
  456. struct avalon7_info *info = avalon7->device_data;
  457. struct pool *pool, *real_pool;
  458. struct pool *pool_stratum0 = &info->pool0;
  459. struct pool *pool_stratum1 = &info->pool1;
  460. struct pool *pool_stratum2 = &info->pool2;
  461. struct thr_info *thr = NULL;
  462. unsigned short expected_crc;
  463. unsigned short actual_crc;
  464. uint32_t nonce, nonce2, ntime, miner, chip_id, tmp;
  465. uint8_t job_id[2];
  466. int pool_no;
  467. uint32_t i;
  468. int64_t last_diff1;
  469. uint16_t vin;
  470. if (likely(avalon7->thr))
  471. thr = avalon7->thr[0];
  472. if (ar->head[0] != AVA7_H1 && ar->head[1] != AVA7_H2) {
  473. applog(LOG_DEBUG, "%s-%d-%d: H1 %02x, H2 %02x",
  474. avalon7->drv->name, avalon7->device_id, modular_id,
  475. ar->head[0], ar->head[1]);
  476. hexdump(ar->data, 32);
  477. return 1;
  478. }
  479. expected_crc = crc16(ar->data, AVA7_P_DATA_LEN);
  480. actual_crc = ((ar->crc[0] & 0xff) << 8) | (ar->crc[1] & 0xff);
  481. if (expected_crc != actual_crc) {
  482. applog(LOG_DEBUG, "%s-%d-%d: %02x: expected crc(%04x), actual_crc(%04x)",
  483. avalon7->drv->name, avalon7->device_id, modular_id,
  484. ar->type, expected_crc, actual_crc);
  485. return 1;
  486. }
  487. switch(ar->type) {
  488. case AVA7_P_NONCE:
  489. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_NONCE", avalon7->drv->name, avalon7->device_id, modular_id);
  490. memcpy(&miner, ar->data + 0, 4);
  491. memcpy(&nonce2, ar->data + 4, 4);
  492. memcpy(&ntime, ar->data + 8, 4);
  493. memcpy(&nonce, ar->data + 12, 4);
  494. job_id[0] = ar->data[16];
  495. job_id[1] = ar->data[17];
  496. pool_no = (ar->data[18] | (ar->data[19] << 8));
  497. miner = be32toh(miner);
  498. chip_id = (miner >> 16) & 0xffff;
  499. miner &= 0xffff;
  500. ntime = be32toh(ntime);
  501. if (miner >= info->miner_count[modular_id] ||
  502. pool_no >= total_pools || pool_no < 0) {
  503. applog(LOG_DEBUG, "%s-%d-%d: Wrong miner/pool_no %d/%d",
  504. avalon7->drv->name, avalon7->device_id, modular_id,
  505. miner, pool_no);
  506. break;
  507. }
  508. nonce2 = be32toh(nonce2);
  509. nonce = be32toh(nonce);
  510. if (ntime > info->max_ntime)
  511. info->max_ntime = ntime;
  512. applog(LOG_DEBUG, "%s-%d-%d: Found! P:%d - N2:%08x N:%08x NR:%d/%d [M:%d - MW: (%"PRIu64",%"PRIu64",%"PRIu64",%"PRIu64")]",
  513. avalon7->drv->name, avalon7->device_id, modular_id,
  514. pool_no, nonce2, nonce, ntime, info->max_ntime,
  515. miner,
  516. info->chip_matching_work[modular_id][miner][0],
  517. info->chip_matching_work[modular_id][miner][1],
  518. info->chip_matching_work[modular_id][miner][2],
  519. info->chip_matching_work[modular_id][miner][3]);
  520. real_pool = pool = pools[pool_no];
  521. if (job_idcmp(job_id, pool->swork.job_id)) {
  522. if (!job_idcmp(job_id, pool_stratum0->swork.job_id)) {
  523. applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum0! (%s)",
  524. avalon7->drv->name, avalon7->device_id, modular_id,
  525. pool_stratum0->swork.job_id);
  526. pool = pool_stratum0;
  527. } else if (!job_idcmp(job_id, pool_stratum1->swork.job_id)) {
  528. applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum1! (%s)",
  529. avalon7->drv->name, avalon7->device_id, modular_id,
  530. pool_stratum1->swork.job_id);
  531. pool = pool_stratum1;
  532. } else if (!job_idcmp(job_id, pool_stratum2->swork.job_id)) {
  533. applog(LOG_DEBUG, "%s-%d-%d: Match to previous stratum2! (%s)",
  534. avalon7->drv->name, avalon7->device_id, modular_id,
  535. pool_stratum2->swork.job_id);
  536. pool = pool_stratum2;
  537. } else {
  538. applog(LOG_ERR, "%s-%d-%d: Cannot match to any stratum! (%s)",
  539. avalon7->drv->name, avalon7->device_id, modular_id,
  540. pool->swork.job_id);
  541. if (likely(thr))
  542. inc_hw_errors(thr);
  543. info->hw_works_i[modular_id][miner]++;
  544. break;
  545. }
  546. }
  547. /* Can happen during init sequence before add_cgpu */
  548. if (unlikely(!thr))
  549. break;
  550. last_diff1 = avalon7->diff1;
  551. if (!submit_nonce2_nonce(thr, pool, real_pool, nonce2, nonce, ntime))
  552. info->hw_works_i[modular_id][miner]++;
  553. else {
  554. info->diff1[modular_id] += (avalon7->diff1 - last_diff1);
  555. info->chip_matching_work[modular_id][miner][chip_id]++;
  556. }
  557. break;
  558. case AVA7_P_STATUS:
  559. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS", avalon7->drv->name, avalon7->device_id, modular_id);
  560. hexdump(ar->data, 32);
  561. memcpy(&tmp, ar->data, 4);
  562. tmp = be32toh(tmp);
  563. info->temp_mm[modular_id] = tmp;
  564. avalon7->temp = decode_auc_temp(info->auc_sensor);
  565. memcpy(&tmp, ar->data + 4, 4);
  566. tmp = be32toh(tmp);
  567. info->fan_cpm[modular_id] = tmp;
  568. memcpy(&tmp, ar->data + 8, 4);
  569. info->local_works_i[modular_id][ar->idx] += be32toh(tmp);
  570. memcpy(&tmp, ar->data + 12, 4);
  571. info->hw_works_i[modular_id][ar->idx] += be32toh(tmp);
  572. memcpy(&tmp, ar->data + 16, 4);
  573. info->error_code[modular_id][ar->idx] = be32toh(tmp);
  574. memcpy(&tmp, ar->data + 20, 4);
  575. info->error_code[modular_id][ar->cnt] = be32toh(tmp);
  576. memcpy(&tmp, ar->data + 24, 4);
  577. info->error_crc[modular_id][ar->idx] += be32toh(tmp);
  578. break;
  579. case AVA7_P_STATUS_PMU:
  580. /* TODO: decode ntc led from PMU */
  581. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS_PMU", avalon7->drv->name, avalon7->device_id, modular_id);
  582. info->power_good[modular_id] = ar->data[16];
  583. for (i = 0; i < AVA7_DEFAULT_PMU_CNT; i++) {
  584. memcpy(&info->pmu_version[modular_id][i], ar->data + 24 + (i * 4), 4);
  585. info->pmu_version[modular_id][i][4] = '\0';
  586. }
  587. for (i = 0; i < info->miner_count[modular_id]; i++) {
  588. memcpy(&vin, ar->data + 8 + i * 2, 2);
  589. info->get_vin[modular_id][i] = decode_vin(info, modular_id, be16toh(vin));
  590. }
  591. break;
  592. case AVA7_P_STATUS_VOLT:
  593. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS_VOLT", avalon7->drv->name, avalon7->device_id, modular_id);
  594. for (i = 0; i < info->miner_count[modular_id]; i++) {
  595. memcpy(&tmp, ar->data + i * 4, 4);
  596. info->get_voltage[modular_id][i] = decode_voltage(info, modular_id, be32toh(tmp));
  597. }
  598. break;
  599. case AVA7_P_STATUS_PLL:
  600. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS_PLL", avalon7->drv->name, avalon7->device_id, modular_id);
  601. for (i = 0; i < AVA7_DEFAULT_PLL_CNT; i++) {
  602. memcpy(&tmp, ar->data + i * 4, 4);
  603. info->get_pll[modular_id][ar->idx][i] = be32toh(tmp);
  604. }
  605. break;
  606. case AVA7_P_STATUS_PVT:
  607. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS_PVT", avalon7->drv->name, avalon7->device_id, modular_id);
  608. for (i = 0; i < info->miner_count[modular_id]; i++) {
  609. memcpy(&tmp, ar->data + i * 8, 4);
  610. tmp = be32toh(tmp);
  611. info->temp[modular_id][i][0] = (tmp >> 24) & 0xff;
  612. info->temp[modular_id][i][1] = (tmp >> 16) & 0xff;
  613. info->temp[modular_id][i][2] = tmp & 0xffff;
  614. memcpy(&tmp, ar->data + (i + 1) * 8 - 4, 4);
  615. tmp = be32toh(tmp);
  616. info->temp[modular_id][i][3] = (tmp >> 16) & 0xffff;
  617. info->temp[modular_id][i][4] = tmp & 0xffff;
  618. /* Update the pvt code to real temperature */
  619. info->temp[modular_id][i][2] = (int)decode_pvt_temp((uint16_t)info->temp[modular_id][i][2]);
  620. info->temp[modular_id][i][3] = (int)decode_pvt_temp((uint16_t)info->temp[modular_id][i][3]);
  621. info->temp[modular_id][i][4] = (int)decode_pvt_temp((uint16_t)info->temp[modular_id][i][4]);
  622. }
  623. break;
  624. case AVA7_P_STATUS_ASIC:
  625. {
  626. int x_miner_id;
  627. int x_asic_id;
  628. if (!info->asic_count[modular_id])
  629. break;
  630. x_miner_id = ar->idx / info->asic_count[modular_id];
  631. x_asic_id = ar->idx % info->asic_count[modular_id];
  632. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS_ASIC %d-%d",
  633. avalon7->drv->name, avalon7->device_id, modular_id,
  634. x_miner_id, x_asic_id);
  635. memcpy(&tmp, ar->data + 0, 4);
  636. if (tmp) {
  637. info->get_asic[modular_id][x_miner_id][x_asic_id][0] = be32toh(tmp);
  638. memcpy(&tmp, ar->data + 4, 4);
  639. info->get_asic[modular_id][x_miner_id][x_asic_id][1] = be32toh(tmp);
  640. memcpy(&tmp, ar->data + 8, 4);
  641. info->get_asic[modular_id][x_miner_id][x_asic_id][2] = be32toh(tmp);
  642. memcpy(&tmp, ar->data + 12, 4);
  643. info->get_asic[modular_id][x_miner_id][x_asic_id][3] = be32toh(tmp);
  644. memcpy(&tmp, ar->data + 16, 4);
  645. info->get_asic[modular_id][x_miner_id][x_asic_id][4] = be32toh(tmp);
  646. }
  647. tmp = *(ar->data + 20);
  648. info->get_asic[modular_id][x_miner_id][x_asic_id][5] = tmp;
  649. tmp = *(ar->data + 21);
  650. info->get_asic[modular_id][x_miner_id][x_asic_id][6] = tmp;
  651. tmp = *(ar->data + 22);
  652. info->get_asic[modular_id][x_miner_id][x_asic_id][7] = tmp;
  653. tmp = *(ar->data + 23);
  654. info->get_asic[modular_id][x_miner_id][x_asic_id][8] = tmp;
  655. tmp = *(ar->data + 24);
  656. info->get_asic[modular_id][x_miner_id][x_asic_id][9] = tmp;
  657. tmp = *(ar->data + 25);
  658. info->get_asic[modular_id][x_miner_id][x_asic_id][10] = tmp;
  659. }
  660. break;
  661. case AVA7_P_STATUS_FAC:
  662. applog(LOG_DEBUG, "%s-%d-%d: AVA7_P_STATUS_FAC", avalon7->drv->name, avalon7->device_id, modular_id);
  663. info->factory_info[0] = ar->data[0];
  664. break;
  665. default:
  666. applog(LOG_DEBUG, "%s-%d-%d: Unknown response %x", avalon7->drv->name, avalon7->device_id, modular_id, ar->type);
  667. break;
  668. }
  669. return 0;
  670. }
  671. /*
  672. # IIC packet format: length[1]+transId[1]+sesId[1]+req[1]+data[60]
  673. # length: 4+len(data)
  674. # transId: 0
  675. # sesId: 0
  676. # req: checkout the header file
  677. # data:
  678. # INIT: clock_rate[4] + reserved[4] + payload[52]
  679. # XFER: txSz[1]+rxSz[1]+options[1]+slaveAddr[1] + payload[56]
  680. */
  681. static int avalon7_auc_init_pkg(uint8_t *iic_pkg, struct avalon7_iic_info *iic_info, uint8_t *buf, int wlen, int rlen)
  682. {
  683. memset(iic_pkg, 0, AVA7_AUC_P_SIZE);
  684. switch (iic_info->iic_op) {
  685. case AVA7_IIC_INIT:
  686. iic_pkg[0] = 12; /* 4 bytes IIC header + 4 bytes speed + 4 bytes xfer delay */
  687. iic_pkg[3] = AVA7_IIC_INIT;
  688. iic_pkg[4] = iic_info->iic_param.aucParam[0] & 0xff;
  689. iic_pkg[5] = (iic_info->iic_param.aucParam[0] >> 8) & 0xff;
  690. iic_pkg[6] = (iic_info->iic_param.aucParam[0] >> 16) & 0xff;
  691. iic_pkg[7] = iic_info->iic_param.aucParam[0] >> 24;
  692. iic_pkg[8] = iic_info->iic_param.aucParam[1] & 0xff;
  693. iic_pkg[9] = (iic_info->iic_param.aucParam[1] >> 8) & 0xff;
  694. iic_pkg[10] = (iic_info->iic_param.aucParam[1] >> 16) & 0xff;
  695. iic_pkg[11] = iic_info->iic_param.aucParam[1] >> 24;
  696. break;
  697. case AVA7_IIC_XFER:
  698. iic_pkg[0] = 8 + wlen;
  699. iic_pkg[3] = AVA7_IIC_XFER;
  700. iic_pkg[4] = wlen;
  701. iic_pkg[5] = rlen;
  702. iic_pkg[7] = iic_info->iic_param.slave_addr;
  703. if (buf && wlen)
  704. memcpy(iic_pkg + 8, buf, wlen);
  705. break;
  706. case AVA7_IIC_RESET:
  707. case AVA7_IIC_DEINIT:
  708. case AVA7_IIC_INFO:
  709. iic_pkg[0] = 4;
  710. iic_pkg[3] = iic_info->iic_op;
  711. break;
  712. default:
  713. break;
  714. }
  715. return 0;
  716. }
  717. static int avalon7_iic_xfer(struct cgpu_info *avalon7, uint8_t slave_addr,
  718. uint8_t *wbuf, int wlen,
  719. uint8_t *rbuf, int rlen)
  720. {
  721. struct avalon7_info *info = avalon7->device_data;
  722. struct i2c_ctx *pctx = NULL;
  723. int err = 1;
  724. bool ret = false;
  725. pctx = info->i2c_slaves[slave_addr];
  726. if (!pctx) {
  727. applog(LOG_ERR, "%s-%d: IIC xfer i2c slaves null!", avalon7->drv->name, avalon7->device_id);
  728. goto out;
  729. }
  730. if (wbuf) {
  731. ret = pctx->write_raw(pctx, wbuf, wlen);
  732. if (!ret) {
  733. applog(LOG_DEBUG, "%s-%d: IIC xfer write raw failed!", avalon7->drv->name, avalon7->device_id);
  734. goto out;
  735. }
  736. }
  737. cgsleep_ms(5);
  738. if (rbuf) {
  739. ret = pctx->read_raw(pctx, rbuf, rlen);
  740. if (!ret) {
  741. applog(LOG_DEBUG, "%s-%d: IIC xfer read raw failed!", avalon7->drv->name, avalon7->device_id);
  742. hexdump(rbuf, rlen);
  743. goto out;
  744. }
  745. }
  746. return 0;
  747. out:
  748. return err;
  749. }
  750. static int avalon7_auc_xfer(struct cgpu_info *avalon7,
  751. uint8_t *wbuf, int wlen, int *write,
  752. uint8_t *rbuf, int rlen, int *read)
  753. {
  754. int err = -1;
  755. if (unlikely(avalon7->usbinfo.nodev))
  756. goto out;
  757. usb_buffer_clear(avalon7);
  758. err = usb_write(avalon7, (char *)wbuf, wlen, write, C_AVA7_WRITE);
  759. if (err || *write != wlen) {
  760. applog(LOG_DEBUG, "%s-%d: AUC xfer %d, w(%d-%d)!", avalon7->drv->name, avalon7->device_id, err, wlen, *write);
  761. usb_nodev(avalon7);
  762. goto out;
  763. }
  764. cgsleep_ms(opt_avalon7_aucxdelay / 4800 + 1);
  765. rlen += 4; /* Add 4 bytes IIC header */
  766. err = usb_read(avalon7, (char *)rbuf, rlen, read, C_AVA7_READ);
  767. if (err || *read != rlen || *read != rbuf[0]) {
  768. applog(LOG_DEBUG, "%s-%d: AUC xfer %d, r(%d-%d-%d)!", avalon7->drv->name, avalon7->device_id, err, rlen - 4, *read, rbuf[0]);
  769. hexdump(rbuf, rlen);
  770. return -1;
  771. }
  772. *read = rbuf[0] - 4; /* Remove 4 bytes IIC header */
  773. out:
  774. return err;
  775. }
  776. static int avalon7_auc_init(struct cgpu_info *avalon7, char *ver)
  777. {
  778. struct avalon7_iic_info iic_info;
  779. int err, wlen, rlen;
  780. uint8_t wbuf[AVA7_AUC_P_SIZE];
  781. uint8_t rbuf[AVA7_AUC_P_SIZE];
  782. if (unlikely(avalon7->usbinfo.nodev))
  783. return 1;
  784. /* Try to clean the AUC buffer */
  785. usb_buffer_clear(avalon7);
  786. err = usb_read(avalon7, (char *)rbuf, AVA7_AUC_P_SIZE, &rlen, C_AVA7_READ);
  787. applog(LOG_DEBUG, "%s-%d: AUC usb_read %d, %d!", avalon7->drv->name, avalon7->device_id, err, rlen);
  788. hexdump(rbuf, AVA7_AUC_P_SIZE);
  789. /* Reset */
  790. iic_info.iic_op = AVA7_IIC_RESET;
  791. rlen = 0;
  792. avalon7_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  793. memset(rbuf, 0, AVA7_AUC_P_SIZE);
  794. err = avalon7_auc_xfer(avalon7, wbuf, AVA7_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  795. if (err) {
  796. applog(LOG_ERR, "%s-%d: Failed to reset Avalon USB2IIC Converter", avalon7->drv->name, avalon7->device_id);
  797. return 1;
  798. }
  799. /* Deinit */
  800. iic_info.iic_op = AVA7_IIC_DEINIT;
  801. rlen = 0;
  802. avalon7_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  803. memset(rbuf, 0, AVA7_AUC_P_SIZE);
  804. err = avalon7_auc_xfer(avalon7, wbuf, AVA7_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  805. if (err) {
  806. applog(LOG_ERR, "%s-%d: Failed to deinit Avalon USB2IIC Converter", avalon7->drv->name, avalon7->device_id);
  807. return 1;
  808. }
  809. /* Init */
  810. iic_info.iic_op = AVA7_IIC_INIT;
  811. iic_info.iic_param.aucParam[0] = opt_avalon7_aucspeed;
  812. iic_info.iic_param.aucParam[1] = opt_avalon7_aucxdelay;
  813. rlen = AVA7_AUC_VER_LEN;
  814. avalon7_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  815. memset(rbuf, 0, AVA7_AUC_P_SIZE);
  816. err = avalon7_auc_xfer(avalon7, wbuf, AVA7_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  817. if (err) {
  818. applog(LOG_ERR, "%s-%d: Failed to init Avalon USB2IIC Converter", avalon7->drv->name, avalon7->device_id);
  819. return 1;
  820. }
  821. hexdump(rbuf, AVA7_AUC_P_SIZE);
  822. memcpy(ver, rbuf + 4, AVA7_AUC_VER_LEN);
  823. ver[AVA7_AUC_VER_LEN] = '\0';
  824. applog(LOG_DEBUG, "%s-%d: USB2IIC Converter version: %s!", avalon7->drv->name, avalon7->device_id, ver);
  825. return 0;
  826. }
  827. static int avalon7_auc_getinfo(struct cgpu_info *avalon7)
  828. {
  829. struct avalon7_iic_info iic_info;
  830. int err, wlen, rlen;
  831. uint8_t wbuf[AVA7_AUC_P_SIZE];
  832. uint8_t rbuf[AVA7_AUC_P_SIZE];
  833. uint8_t *pdata = rbuf + 4;
  834. uint16_t adc_val;
  835. struct avalon7_info *info = avalon7->device_data;
  836. iic_info.iic_op = AVA7_IIC_INFO;
  837. /* Device info: (9 bytes)
  838. * tempadc(2), reqRdIndex, reqWrIndex,
  839. * respRdIndex, respWrIndex, tx_flags, state
  840. * */
  841. rlen = 7;
  842. avalon7_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  843. memset(rbuf, 0, AVA7_AUC_P_SIZE);
  844. err = avalon7_auc_xfer(avalon7, wbuf, AVA7_AUC_P_SIZE, &wlen, rbuf, rlen, &rlen);
  845. if (err) {
  846. applog(LOG_ERR, "%s-%d: AUC Failed to get info ", avalon7->drv->name, avalon7->device_id);
  847. return 1;
  848. }
  849. applog(LOG_DEBUG, "%s-%d: AUC tempADC(%03d), reqcnt(%d), respcnt(%d), txflag(%d), state(%d)",
  850. avalon7->drv->name, avalon7->device_id,
  851. pdata[1] << 8 | pdata[0],
  852. pdata[2],
  853. pdata[3],
  854. pdata[5] << 8 | pdata[4],
  855. pdata[6]);
  856. adc_val = pdata[1] << 8 | pdata[0];
  857. info->auc_sensor = 3.3 * adc_val * 10000 / 1023;
  858. return 0;
  859. }
  860. static int avalon7_iic_xfer_pkg(struct cgpu_info *avalon7, uint8_t slave_addr,
  861. const struct avalon7_pkg *pkg, struct avalon7_ret *ret)
  862. {
  863. struct avalon7_iic_info iic_info;
  864. int err, wcnt, rcnt, rlen = 0;
  865. uint8_t wbuf[AVA7_AUC_P_SIZE];
  866. uint8_t rbuf[AVA7_AUC_P_SIZE];
  867. struct avalon7_info *info = avalon7->device_data;
  868. if (ret)
  869. rlen = AVA7_READ_SIZE;
  870. if (info->connecter == AVA7_CONNECTER_AUC) {
  871. if (unlikely(avalon7->usbinfo.nodev))
  872. return AVA7_SEND_ERROR;
  873. iic_info.iic_op = AVA7_IIC_XFER;
  874. iic_info.iic_param.slave_addr = slave_addr;
  875. avalon7_auc_init_pkg(wbuf, &iic_info, (uint8_t *)pkg, AVA7_WRITE_SIZE, rlen);
  876. err = avalon7_auc_xfer(avalon7, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt);
  877. if ((pkg->type != AVA7_P_DETECT) && err == -7 && !rcnt && rlen) {
  878. avalon7_auc_init_pkg(wbuf, &iic_info, NULL, 0, rlen);
  879. err = avalon7_auc_xfer(avalon7, wbuf, wbuf[0], &wcnt, rbuf, rlen, &rcnt);
  880. applog(LOG_DEBUG, "%s-%d-%d: AUC read again!(type:0x%x, err:%d)", avalon7->drv->name, avalon7->device_id, slave_addr, pkg->type, err);
  881. }
  882. if (err || rcnt != rlen) {
  883. if (info->xfer_err_cnt++ == 100) {
  884. applog(LOG_DEBUG, "%s-%d-%d: AUC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d",
  885. avalon7->drv->name, avalon7->device_id, slave_addr,
  886. err, rcnt, rlen);
  887. cgsleep_ms(5 * 1000); /* Wait MM reset */
  888. if (avalon7_auc_init(avalon7, info->auc_version)) {
  889. applog(LOG_WARNING, "%s-%d: Failed to re-init auc, unplugging for new hotplug",
  890. avalon7->drv->name, avalon7->device_id);
  891. usb_nodev(avalon7);
  892. }
  893. }
  894. return AVA7_SEND_ERROR;
  895. }
  896. if (ret)
  897. memcpy((char *)ret, rbuf + 4, AVA7_READ_SIZE);
  898. info->xfer_err_cnt = 0;
  899. }
  900. if (info->connecter == AVA7_CONNECTER_IIC) {
  901. err = avalon7_iic_xfer(avalon7, slave_addr, (uint8_t *)pkg, AVA7_WRITE_SIZE, (uint8_t *)ret, AVA7_READ_SIZE);
  902. if ((pkg->type != AVA7_P_DETECT) && err) {
  903. err = avalon7_iic_xfer(avalon7, slave_addr, (uint8_t *)pkg, AVA7_WRITE_SIZE, (uint8_t *)ret, AVA7_READ_SIZE);
  904. applog(LOG_DEBUG, "%s-%d-%d: IIC read again!(type:0x%x, err:%d)", avalon7->drv->name, avalon7->device_id, slave_addr, pkg->type, err);
  905. }
  906. if (err) {
  907. /* FIXME: Don't care broadcast message with no reply, or it will block other thread when called by avalon7_send_bc_pkgs */
  908. if ((pkg->type != AVA7_P_DETECT) && (slave_addr == AVA7_MODULE_BROADCAST))
  909. return AVA7_SEND_OK;
  910. if (info->xfer_err_cnt++ == 100) {
  911. info->xfer_err_cnt = 0;
  912. applog(LOG_DEBUG, "%s-%d-%d: IIC xfer_err_cnt reach err = %d, rcnt = %d, rlen = %d",
  913. avalon7->drv->name, avalon7->device_id, slave_addr,
  914. err, rcnt, rlen);
  915. cgsleep_ms(5 * 1000); /* Wait MM reset */
  916. }
  917. return AVA7_SEND_ERROR;
  918. }
  919. info->xfer_err_cnt = 0;
  920. }
  921. return AVA7_SEND_OK;
  922. }
  923. static int avalon7_send_bc_pkgs(struct cgpu_info *avalon7, const struct avalon7_pkg *pkg)
  924. {
  925. int ret;
  926. do {
  927. ret = avalon7_iic_xfer_pkg(avalon7, AVA7_MODULE_BROADCAST, pkg, NULL);
  928. } while (ret != AVA7_SEND_OK);
  929. return 0;
  930. }
  931. static void avalon7_stratum_pkgs(struct cgpu_info *avalon7, struct pool *pool)
  932. {
  933. struct avalon7_info *info = avalon7->device_data;
  934. const int merkle_offset = 36;
  935. struct avalon7_pkg pkg;
  936. int i, a, b;
  937. uint32_t tmp;
  938. unsigned char target[32];
  939. int job_id_len, n2size;
  940. unsigned short crc;
  941. int coinbase_len_posthash, coinbase_len_prehash;
  942. uint8_t coinbase_prehash[32];
  943. uint32_t range, start;
  944. /* Send out the first stratum message STATIC */
  945. applog(LOG_DEBUG, "%s-%d: Pool stratum message STATIC: %d, %d, %d, %d, %d",
  946. avalon7->drv->name, avalon7->device_id,
  947. pool->coinbase_len,
  948. pool->nonce2_offset,
  949. pool->n2size,
  950. merkle_offset,
  951. pool->merkles);
  952. memset(pkg.data, 0, AVA7_P_DATA_LEN);
  953. tmp = be32toh(pool->coinbase_len);
  954. memcpy(pkg.data, &tmp, 4);
  955. tmp = be32toh(pool->nonce2_offset);
  956. memcpy(pkg.data + 4, &tmp, 4);
  957. n2size = pool->n2size >= 4 ? 4 : pool->n2size;
  958. tmp = be32toh(n2size);
  959. memcpy(pkg.data + 8, &tmp, 4);
  960. tmp = be32toh(merkle_offset);
  961. memcpy(pkg.data + 12, &tmp, 4);
  962. tmp = be32toh(pool->merkles);
  963. memcpy(pkg.data + 16, &tmp, 4);
  964. if (pool->n2size == 3)
  965. range = 0xffffff / (total_devices ? total_devices : 1);
  966. else
  967. range = 0xffffffff / (total_devices ? total_devices : 1);
  968. start = range * avalon7->device_id;
  969. tmp = be32toh(start);
  970. memcpy(pkg.data + 20, &tmp, 4);
  971. tmp = be32toh(range);
  972. memcpy(pkg.data + 24, &tmp, 4);
  973. if (info->work_restart) {
  974. info->work_restart = false;
  975. tmp = be32toh(0x1);
  976. memcpy(pkg.data + 28, &tmp, 4);
  977. }
  978. avalon7_init_pkg(&pkg, AVA7_P_STATIC, 1, 1);
  979. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  980. return;
  981. if (pool->sdiff <= AVA7_DRV_DIFFMAX)
  982. set_target(target, pool->sdiff);
  983. else
  984. set_target(target, AVA7_DRV_DIFFMAX);
  985. memcpy(pkg.data, target, 32);
  986. if (opt_debug) {
  987. char *target_str;
  988. target_str = bin2hex(target, 32);
  989. applog(LOG_DEBUG, "%s-%d: Pool stratum target: %s", avalon7->drv->name, avalon7->device_id, target_str);
  990. free(target_str);
  991. }
  992. avalon7_init_pkg(&pkg, AVA7_P_TARGET, 1, 1);
  993. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  994. return;
  995. memset(pkg.data, 0, AVA7_P_DATA_LEN);
  996. job_id_len = strlen(pool->swork.job_id);
  997. crc = crc16((unsigned char *)pool->swork.job_id, job_id_len);
  998. applog(LOG_DEBUG, "%s-%d: Pool stratum message JOBS_ID[%04x]: %s",
  999. avalon7->drv->name, avalon7->device_id,
  1000. crc, pool->swork.job_id);
  1001. tmp = ((crc << 16) | pool->pool_no);
  1002. if (info->last_jobid != tmp) {
  1003. info->last_jobid = tmp;
  1004. pkg.data[0] = (crc & 0xff00) >> 8;
  1005. pkg.data[1] = crc & 0xff;
  1006. pkg.data[2] = pool->pool_no & 0xff;
  1007. pkg.data[3] = (pool->pool_no & 0xff00) >> 8;
  1008. avalon7_init_pkg(&pkg, AVA7_P_JOB_ID, 1, 1);
  1009. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  1010. return;
  1011. }
  1012. coinbase_len_prehash = pool->nonce2_offset - (pool->nonce2_offset % SHA256_BLOCK_SIZE);
  1013. coinbase_len_posthash = pool->coinbase_len - coinbase_len_prehash;
  1014. sha256_prehash(pool->coinbase, coinbase_len_prehash, coinbase_prehash);
  1015. a = (coinbase_len_posthash / AVA7_P_DATA_LEN) + 1;
  1016. b = coinbase_len_posthash % AVA7_P_DATA_LEN;
  1017. memcpy(pkg.data, coinbase_prehash, 32);
  1018. avalon7_init_pkg(&pkg, AVA7_P_COINBASE, 1, a + (b ? 1 : 0));
  1019. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  1020. return;
  1021. applog(LOG_DEBUG, "%s-%d: Pool stratum message modified COINBASE: %d %d",
  1022. avalon7->drv->name, avalon7->device_id,
  1023. a, b);
  1024. for (i = 1; i < a; i++) {
  1025. memcpy(pkg.data, pool->coinbase + coinbase_len_prehash + i * 32 - 32, 32);
  1026. avalon7_init_pkg(&pkg, AVA7_P_COINBASE, i + 1, a + (b ? 1 : 0));
  1027. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  1028. return;
  1029. }
  1030. if (b) {
  1031. memset(pkg.data, 0, AVA7_P_DATA_LEN);
  1032. memcpy(pkg.data, pool->coinbase + coinbase_len_prehash + i * 32 - 32, b);
  1033. avalon7_init_pkg(&pkg, AVA7_P_COINBASE, i + 1, i + 1);
  1034. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  1035. return;
  1036. }
  1037. b = pool->merkles;
  1038. applog(LOG_DEBUG, "%s-%d: Pool stratum message MERKLES: %d", avalon7->drv->name, avalon7->device_id, b);
  1039. for (i = 0; i < b; i++) {
  1040. memset(pkg.data, 0, AVA7_P_DATA_LEN);
  1041. memcpy(pkg.data, pool->swork.merkle_bin[i], 32);
  1042. avalon7_init_pkg(&pkg, AVA7_P_MERKLES, i + 1, b);
  1043. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  1044. return;
  1045. }
  1046. applog(LOG_DEBUG, "%s-%d: Pool stratum message HEADER: 4", avalon7->drv->name, avalon7->device_id);
  1047. for (i = 0; i < 4; i++) {
  1048. memset(pkg.data, 0, AVA7_P_DATA_LEN);
  1049. memcpy(pkg.data, pool->header_bin + i * 32, 32);
  1050. avalon7_init_pkg(&pkg, AVA7_P_HEADER, i + 1, 4);
  1051. if (avalon7_send_bc_pkgs(avalon7, &pkg))
  1052. return;
  1053. }
  1054. if (info->connecter == AVA7_CONNECTER_AUC)
  1055. avalon7_auc_getinfo(avalon7);
  1056. }
  1057. static struct cgpu_info *avalon7_iic_detect(void)
  1058. {
  1059. int i;
  1060. struct avalon7_info *info;
  1061. struct cgpu_info *avalon7 = NULL;
  1062. struct i2c_ctx *i2c_slave = NULL;
  1063. i2c_slave = i2c_slave_open(I2C_BUS, 0);
  1064. if (!i2c_slave) {
  1065. applog(LOG_ERR, "avalon7 init iic failed\n");
  1066. return NULL;
  1067. }
  1068. i2c_slave->exit(i2c_slave);
  1069. i2c_slave = NULL;
  1070. avalon7 = cgcalloc(1, sizeof(*avalon7));
  1071. avalon7->drv = &avalon7_drv;
  1072. avalon7->deven = DEV_ENABLED;
  1073. avalon7->threads = 1;
  1074. add_cgpu(avalon7);
  1075. applog(LOG_INFO, "%s-%d: Found at %s", avalon7->drv->name, avalon7->device_id,
  1076. I2C_BUS);
  1077. avalon7->device_data = cgcalloc(sizeof(struct avalon7_info), 1);
  1078. memset(avalon7->device_data, 0, sizeof(struct avalon7_info));
  1079. info = avalon7->device_data;
  1080. for (i = 0; i < AVA7_DEFAULT_MODULARS; i++) {
  1081. info->enable[i] = false;
  1082. info->reboot[i] = false;
  1083. info->i2c_slaves[i] = i2c_slave_open(I2C_BUS, i);
  1084. if (!info->i2c_slaves[i]) {
  1085. applog(LOG_ERR, "avalon7 init i2c slaves failed\n");
  1086. free(avalon7->device_data);
  1087. avalon7->device_data = NULL;
  1088. free(avalon7);
  1089. avalon7 = NULL;
  1090. return NULL;
  1091. }
  1092. }
  1093. info->connecter = AVA7_CONNECTER_IIC;
  1094. return avalon7;
  1095. }
  1096. static void detect_modules(struct cgpu_info *avalon7);
  1097. static struct cgpu_info *avalon7_auc_detect(struct libusb_device *dev, struct usb_find_devices *found)
  1098. {
  1099. int i, modules = 0;
  1100. struct avalon7_info *info;
  1101. struct cgpu_info *avalon7 = usb_alloc_cgpu(&avalon7_drv, 1);
  1102. char auc_ver[AVA7_AUC_VER_LEN];
  1103. if (!usb_init(avalon7, dev, found)) {
  1104. applog(LOG_ERR, "avalon7 failed usb_init");
  1105. avalon7 = usb_free_cgpu(avalon7);
  1106. return NULL;
  1107. }
  1108. /* avalon7 prefers not to use zero length packets */
  1109. avalon7->nozlp = true;
  1110. /* We try twice on AUC init */
  1111. if (avalon7_auc_init(avalon7, auc_ver) && avalon7_auc_init(avalon7, auc_ver))
  1112. return NULL;
  1113. applog(LOG_INFO, "%s-%d: Found at %s", avalon7->drv->name, avalon7->device_id,
  1114. avalon7->device_path);
  1115. avalon7->device_data = cgcalloc(sizeof(struct avalon7_info), 1);
  1116. memset(avalon7->device_data, 0, sizeof(struct avalon7_info));
  1117. info = avalon7->device_data;
  1118. memcpy(info->auc_version, auc_ver, AVA7_AUC_VER_LEN);
  1119. info->auc_version[AVA7_AUC_VER_LEN] = '\0';
  1120. info->auc_speed = opt_avalon7_aucspeed;
  1121. info->auc_xdelay = opt_avalon7_aucxdelay;
  1122. for (i = 0; i < AVA7_DEFAULT_MODULARS; i++)
  1123. info->enable[i] = 0;
  1124. info->connecter = AVA7_CONNECTER_AUC;
  1125. detect_modules(avalon7);
  1126. for (i = 0; i < AVA7_DEFAULT_MODULARS; i++)
  1127. modules += info->enable[i];
  1128. if (!modules) {
  1129. applog(LOG_INFO, "avalon7 found but no modules initialised");
  1130. free(info);
  1131. avalon7 = usb_free_cgpu(avalon7);
  1132. return NULL;
  1133. }
  1134. /* We have an avalon7 AUC connected */
  1135. avalon7->threads = 1;
  1136. add_cgpu(avalon7);
  1137. update_usb_stats(avalon7);
  1138. return avalon7;
  1139. }
  1140. static inline void avalon7_detect(bool __maybe_unused hotplug)
  1141. {
  1142. usb_detect(&avalon7_drv, avalon7_auc_detect);
  1143. if (!hotplug && opt_avalon7_iic_detect)
  1144. avalon7_iic_detect();
  1145. }
  1146. static bool avalon7_prepare(struct thr_info *thr)
  1147. {
  1148. struct cgpu_info *avalon7 = thr->cgpu;
  1149. struct avalon7_info *info = avalon7->device_data;
  1150. info->last_diff1 = 0;
  1151. info->pending_diff1 = 0;
  1152. info->last_rej = 0;
  1153. info->mm_count = 0;
  1154. info->xfer_err_cnt = 0;
  1155. info->pool_no = 0;
  1156. memset(&(info->firsthash), 0, sizeof(info->firsthash));
  1157. cgtime(&(info->last_fan_adj));
  1158. cgtime(&info->last_stratum);
  1159. cgtime(&info->last_detect);
  1160. cglock_init(&info->update_lock);
  1161. cglock_init(&info->pool0.data_lock);
  1162. cglock_init(&info->pool1.data_lock);
  1163. cglock_init(&info->pool2.data_lock);
  1164. return true;
  1165. }
  1166. static int check_module_exist(struct cgpu_info *avalon7, uint8_t mm_dna[AVA7_MM_DNA_LEN])
  1167. {
  1168. struct avalon7_info *info = avalon7->device_data;
  1169. int i;
  1170. for (i = 0; i < AVA7_DEFAULT_MODULARS; i++) {
  1171. /* last byte is \0 */
  1172. if (info->enable[i] && !memcmp(info->mm_dna[i], mm_dna, AVA7_MM_DNA_LEN))
  1173. return 1;
  1174. }
  1175. return 0;
  1176. }
  1177. static void detect_modules(struct cgpu_info *avalon7)
  1178. {
  1179. struct avalon7_info *info = avalon7->device_data;
  1180. struct avalon7_pkg send_pkg;
  1181. struct avalon7_ret ret_pkg;
  1182. uint32_t tmp;
  1183. int i, j, k, err, rlen;
  1184. uint8_t dev_index;
  1185. uint8_t rbuf[AVA7_AUC_P_SIZE];
  1186. /* Detect new modules here */
  1187. for (i = 1; i < AVA7_DEFAULT_MODULARS + 1; i++) {
  1188. if (info->enable[i])
  1189. continue;
  1190. /* Send out detect pkg */
  1191. applog(LOG_DEBUG, "%s-%d: AVA7_P_DETECT ID[%d]",
  1192. avalon7->drv->name, avalon7->device_id, i);
  1193. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1194. tmp = be32toh(i); /* ID */
  1195. memcpy(send_pkg.data + 28, &tmp, 4);
  1196. avalon7_init_pkg(&send_pkg, AVA7_P_DETECT, 1, 1);
  1197. err = avalon7_iic_xfer_pkg(avalon7, AVA7_MODULE_BROADCAST, &send_pkg, &ret_pkg);
  1198. if (err == AVA7_SEND_OK) {
  1199. if (decode_pkg(avalon7, &ret_pkg, AVA7_MODULE_BROADCAST)) {
  1200. applog(LOG_DEBUG, "%s-%d: Should be AVA7_P_ACKDETECT(%d), but %d",
  1201. avalon7->drv->name, avalon7->device_id, AVA7_P_ACKDETECT, ret_pkg.type);
  1202. continue;
  1203. }
  1204. }
  1205. if (err != AVA7_SEND_OK) {
  1206. applog(LOG_DEBUG, "%s-%d: AVA7_P_DETECT: Failed AUC xfer data with err %d",
  1207. avalon7->drv->name, avalon7->device_id, err);
  1208. break;
  1209. }
  1210. applog(LOG_DEBUG, "%s-%d: Module detect ID[%d]: %d",
  1211. avalon7->drv->name, avalon7->device_id, i, ret_pkg.type);
  1212. if (ret_pkg.type != AVA7_P_ACKDETECT)
  1213. break;
  1214. if (check_module_exist(avalon7, ret_pkg.data))
  1215. continue;
  1216. /* Check count of modulars */
  1217. if (i == AVA7_DEFAULT_MODULARS) {
  1218. applog(LOG_NOTICE, "You have connected more than %d machines. This is discouraged.", (AVA7_DEFAULT_MODULARS - 1));
  1219. info->conn_overloaded = true;
  1220. break;
  1221. } else
  1222. info->conn_overloaded = false;
  1223. memcpy(info->mm_version[i], ret_pkg.data + AVA7_MM_DNA_LEN, AVA7_MM_VER_LEN);
  1224. info->mm_version[i][AVA7_MM_VER_LEN] = '\0';
  1225. for (dev_index = 0; dev_index < (sizeof(avalon7_dev_table) / sizeof(avalon7_dev_table[0])); dev_index++) {
  1226. if (!strncmp((char *)&(info->mm_version[i]), (char *)(avalon7_dev_table[dev_index].dev_id_str), 3)) {
  1227. info->mod_type[i] = avalon7_dev_table[dev_index].mod_type;
  1228. info->miner_count[i] = avalon7_dev_table[dev_index].miner_count;
  1229. info->asic_count[i] = avalon7_dev_table[dev_index].asic_count;
  1230. info->vin_adc_ratio[i] = avalon7_dev_table[dev_index].vin_adc_ratio;
  1231. info->vout_adc_ratio[i] = avalon7_dev_table[dev_index].vout_adc_ratio;
  1232. break;
  1233. }
  1234. }
  1235. if (dev_index == (sizeof(avalon7_dev_table) / sizeof(avalon7_dev_table[0]))) {
  1236. applog(LOG_NOTICE, "%s-%d: The modular version %s cann't be support",
  1237. avalon7->drv->name, avalon7->device_id, info->mm_version[i]);
  1238. break;
  1239. }
  1240. info->enable[i] = 1;
  1241. cgtime(&info->elapsed[i]);
  1242. memcpy(info->mm_dna[i], ret_pkg.data, AVA7_MM_DNA_LEN);
  1243. memcpy(&tmp, ret_pkg.data + AVA7_MM_DNA_LEN + AVA7_MM_VER_LEN, 4);
  1244. tmp = be32toh(tmp);
  1245. info->total_asics[i] = tmp;
  1246. info->temp_overheat[i] = AVA7_DEFAULT_TEMP_OVERHEAT;
  1247. info->temp_target[i] = opt_avalon7_temp_target;
  1248. info->fan_pct[i] = opt_avalon7_fan_min;
  1249. for (j = 0; j < info->miner_count[i]; j++) {
  1250. if (opt_avalon7_voltage == AVA7_INVALID_VOLTAGE)
  1251. info->set_voltage[i][j] = avalon7_dev_table[dev_index].set_voltage;
  1252. else
  1253. info->set_voltage[i][j] = opt_avalon7_voltage;
  1254. info->get_voltage[i][j] = 0;
  1255. info->get_vin[i][j] = 0;
  1256. for (k = 0; k < 5; k++)
  1257. info->temp[i][j][k] = -273;
  1258. }
  1259. info->freq_mode[i] = AVA7_FREQ_INIT_MODE;
  1260. memset(info->set_frequency[i], 0, sizeof(unsigned int) * info->miner_count[i] * AVA7_DEFAULT_PLL_CNT);
  1261. memset(info->get_pll[i], 0, sizeof(uint32_t) * info->miner_count[i] * AVA7_DEFAULT_PLL_CNT);
  1262. memset(info->get_asic[i], 0, sizeof(uint32_t) * 11 * info->miner_count[i] * AVA7_DEFAULT_PLL_CNT);
  1263. info->led_indicator[i] = 0;
  1264. info->cutoff[i] = 0;
  1265. info->fan_cpm[i] = 0;
  1266. info->temp_mm[i] = -273;
  1267. info->temp_last_max[i] = -273;
  1268. info->local_works[i] = 0;
  1269. info->hw_works[i] = 0;
  1270. for (j = 0; j < info->miner_count[i]; j++) {
  1271. memset(info->chip_matching_work[i][j], 0, sizeof(uint64_t) * info->asic_count[i]);
  1272. info->local_works_i[i][j] = 0;
  1273. info->hw_works_i[i][j] = 0;
  1274. info->error_code[i][j] = 0;
  1275. info->error_crc[i][j] = 0;
  1276. }
  1277. info->error_code[i][j] = 0;
  1278. info->error_polling_cnt[i] = 0;
  1279. info->power_good[i] = 0;
  1280. memset(info->pmu_version[i], 0, sizeof(char) * 5 * AVA7_DEFAULT_PMU_CNT);
  1281. info->diff1[i] = 0;
  1282. applog(LOG_NOTICE, "%s-%d: New module detected! ID[%d-%x]",
  1283. avalon7->drv->name, avalon7->device_id, i, info->mm_dna[i][AVA7_MM_DNA_LEN - 1]);
  1284. /* Tell MM, it has been detected */
  1285. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1286. memcpy(send_pkg.data, info->mm_dna[i], AVA7_MM_DNA_LEN);
  1287. avalon7_init_pkg(&send_pkg, AVA7_P_SYNC, 1, 1);
  1288. avalon7_iic_xfer_pkg(avalon7, i, &send_pkg, &ret_pkg);
  1289. /* Keep the usb buffer is empty */
  1290. usb_buffer_clear(avalon7);
  1291. usb_read(avalon7, (char *)rbuf, AVA7_AUC_P_SIZE, &rlen, C_AVA7_READ);
  1292. }
  1293. }
  1294. static void detach_module(struct cgpu_info *avalon7, int addr)
  1295. {
  1296. struct avalon7_info *info = avalon7->device_data;
  1297. info->enable[addr] = 0;
  1298. applog(LOG_NOTICE, "%s-%d: Module detached! ID[%d]",
  1299. avalon7->drv->name, avalon7->device_id, addr);
  1300. }
  1301. static int polling(struct cgpu_info *avalon7)
  1302. {
  1303. struct avalon7_info *info = avalon7->device_data;
  1304. struct avalon7_pkg send_pkg;
  1305. struct avalon7_ret ar;
  1306. int i, tmp, ret, decode_err = 0;
  1307. struct timeval current_fan;
  1308. int do_adjust_fan = 0;
  1309. uint32_t fan_pwm;
  1310. double device_tdiff;
  1311. cgtime(&current_fan);
  1312. device_tdiff = tdiff(&current_fan, &(info->last_fan_adj));
  1313. if (device_tdiff > 2.0 || device_tdiff < 0) {
  1314. cgtime(&info->last_fan_adj);
  1315. do_adjust_fan = 1;
  1316. }
  1317. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  1318. if (!info->enable[i])
  1319. continue;
  1320. cgsleep_ms(opt_avalon7_polling_delay);
  1321. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1322. /* Red LED */
  1323. tmp = be32toh(info->led_indicator[i]);
  1324. memcpy(send_pkg.data, &tmp, 4);
  1325. /* Adjust fan every 2 seconds*/
  1326. if (do_adjust_fan) {
  1327. fan_pwm = adjust_fan(info, i);
  1328. fan_pwm |= 0x80000000;
  1329. tmp = be32toh(fan_pwm);
  1330. memcpy(send_pkg.data + 4, &tmp, 4);
  1331. }
  1332. if (info->reboot[i]) {
  1333. info->reboot[i] = false;
  1334. send_pkg.data[8] = 0x1;
  1335. }
  1336. avalon7_init_pkg(&send_pkg, AVA7_P_POLLING, 1, 1);
  1337. ret = avalon7_iic_xfer_pkg(avalon7, i, &send_pkg, &ar);
  1338. if (ret == AVA7_SEND_OK)
  1339. decode_err = decode_pkg(avalon7, &ar, i);
  1340. if (ret != AVA7_SEND_OK || decode_err) {
  1341. info->error_polling_cnt[i]++;
  1342. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1343. avalon7_init_pkg(&send_pkg, AVA7_P_RSTMMTX, 1, 1);
  1344. avalon7_iic_xfer_pkg(avalon7, i, &send_pkg, NULL);
  1345. if (info->error_polling_cnt[i] >= 10)
  1346. detach_module(avalon7, i);
  1347. }
  1348. if (ret == AVA7_SEND_OK && !decode_err) {
  1349. info->error_polling_cnt[i] = 0;
  1350. if ((ar.opt == AVA7_P_STATUS) &&
  1351. (info->mm_dna[i][AVA7_MM_DNA_LEN - 1] != ar.opt)) {
  1352. applog(LOG_ERR, "%s-%d-%d: Dup address found %d-%d",
  1353. avalon7->drv->name, avalon7->device_id, i,
  1354. info->mm_dna[i][AVA7_MM_DNA_LEN - 1], ar.opt);
  1355. hexdump((uint8_t *)&ar, sizeof(ar));
  1356. detach_module(avalon7, i);
  1357. }
  1358. }
  1359. }
  1360. return 0;
  1361. }
  1362. static void copy_pool_stratum(struct pool *pool_stratum, struct pool *pool)
  1363. {
  1364. int i;
  1365. int merkles = pool->merkles, job_id_len;
  1366. size_t coinbase_len = pool->coinbase_len;
  1367. unsigned short crc;
  1368. if (!pool->swork.job_id)
  1369. return;
  1370. if (pool_stratum->swork.job_id) {
  1371. job_id_len = strlen(pool->swork.job_id);
  1372. crc = crc16((unsigned char *)pool->swork.job_id, job_id_len);
  1373. job_id_len = strlen(pool_stratum->swork.job_id);
  1374. if (crc16((unsigned char *)pool_stratum->swork.job_id, job_id_len) == crc)
  1375. return;
  1376. }
  1377. cg_wlock(&pool_stratum->data_lock);
  1378. free(pool_stratum->swork.job_id);
  1379. free(pool_stratum->nonce1);
  1380. free(pool_stratum->coinbase);
  1381. pool_stratum->coinbase = cgcalloc(coinbase_len, 1);
  1382. memcpy(pool_stratum->coinbase, pool->coinbase, coinbase_len);
  1383. for (i = 0; i < pool_stratum->merkles; i++)
  1384. free(pool_stratum->swork.merkle_bin[i]);
  1385. if (merkles) {
  1386. pool_stratum->swork.merkle_bin = cgrealloc(pool_stratum->swork.merkle_bin,
  1387. sizeof(char *) * merkles + 1);
  1388. for (i = 0; i < merkles; i++) {
  1389. pool_stratum->swork.merkle_bin[i] = cgmalloc(32);
  1390. memcpy(pool_stratum->swork.merkle_bin[i], pool->swork.merkle_bin[i], 32);
  1391. }
  1392. }
  1393. pool_stratum->sdiff = pool->sdiff;
  1394. pool_stratum->coinbase_len = pool->coinbase_len;
  1395. pool_stratum->nonce2_offset = pool->nonce2_offset;
  1396. pool_stratum->n2size = pool->n2size;
  1397. pool_stratum->merkles = pool->merkles;
  1398. pool_stratum->swork.job_id = strdup(pool->swork.job_id);
  1399. pool_stratum->nonce1 = strdup(pool->nonce1);
  1400. memcpy(pool_stratum->ntime, pool->ntime, sizeof(pool_stratum->ntime));
  1401. memcpy(pool_stratum->header_bin, pool->header_bin, sizeof(pool_stratum->header_bin));
  1402. cg_wunlock(&pool_stratum->data_lock);
  1403. }
  1404. static void avalon7_init_setting(struct cgpu_info *avalon7, int addr)
  1405. {
  1406. struct avalon7_pkg send_pkg;
  1407. uint32_t tmp;
  1408. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1409. /* TODO:ss/ssp mode */
  1410. tmp = be32toh(opt_avalon7_freq_sel);
  1411. memcpy(send_pkg.data + 4, &tmp, 4);
  1412. /* adjust flag [0-5]: reserved, 6: nonce check, 7: autof*/
  1413. tmp = 1;
  1414. if (!opt_avalon7_smart_speed)
  1415. tmp = 0;
  1416. tmp |= (1 << 1); /* Enable nonce check */
  1417. tmp |= (opt_avalon7_asic_debug << 2);
  1418. send_pkg.data[8] = tmp & 0xff;
  1419. send_pkg.data[9] = opt_avalon7_nonce_mask & 0xff;
  1420. /* Package the data */
  1421. avalon7_init_pkg(&send_pkg, AVA7_P_SET, 1, 1);
  1422. if (addr == AVA7_MODULE_BROADCAST)
  1423. avalon7_send_bc_pkgs(avalon7, &send_pkg);
  1424. else
  1425. avalon7_iic_xfer_pkg(avalon7, addr, &send_pkg, NULL);
  1426. }
  1427. static void avalon7_set_voltage(struct cgpu_info *avalon7, int addr, unsigned int voltage[])
  1428. {
  1429. struct avalon7_info *info = avalon7->device_data;
  1430. struct avalon7_pkg send_pkg;
  1431. uint32_t tmp;
  1432. uint8_t i;
  1433. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1434. /* FIXME: miner_count should <= 8 */
  1435. for (i = 0; i < info->miner_count[addr]; i++) {
  1436. tmp = be32toh(encode_voltage(voltage[i] +
  1437. opt_avalon7_voltage_offset * AVA7_DEFAULT_VOLTAGE_STEP));
  1438. memcpy(send_pkg.data + i * 4, &tmp, 4);
  1439. }
  1440. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set voltage miner %d, (%d-%d)",
  1441. avalon7->drv->name, avalon7->device_id, addr,
  1442. i, voltage[0], voltage[info->miner_count[addr] - 1]);
  1443. /* Package the data */
  1444. avalon7_init_pkg(&send_pkg, AVA7_P_SET_VOLT, 1, 1);
  1445. if (addr == AVA7_MODULE_BROADCAST)
  1446. avalon7_send_bc_pkgs(avalon7, &send_pkg);
  1447. else
  1448. avalon7_iic_xfer_pkg(avalon7, addr, &send_pkg, NULL);
  1449. }
  1450. static void avalon7_set_freq(struct cgpu_info *avalon7, int addr, int miner_id, unsigned int freq[])
  1451. {
  1452. struct avalon7_info *info = avalon7->device_data;
  1453. struct avalon7_pkg send_pkg;
  1454. uint32_t tmp, f;
  1455. uint8_t i;
  1456. send_pkg.idx = 0; /* TODO: This is only for broadcast to all miners
  1457. * This should be support 4 miners */
  1458. send_pkg.cnt = info->miner_count[addr];
  1459. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1460. for (i = 0; i < AVA7_DEFAULT_PLL_CNT; i++) {
  1461. tmp = be32toh(api_get_cpm(freq[i]));
  1462. memcpy(send_pkg.data + i * 4, &tmp, 4);
  1463. }
  1464. f = freq[0];
  1465. for (i = 1; i < AVA7_DEFAULT_PLL_CNT; i++)
  1466. f = f > freq[i] ? f : freq[i];
  1467. tmp = ((AVA7_ASIC_TIMEOUT_CONST / f) * 40 / 4);
  1468. tmp = be32toh(tmp);
  1469. memcpy(send_pkg.data + AVA7_DEFAULT_PLL_CNT * 4, &tmp, 4);
  1470. tmp = AVA7_ASIC_TIMEOUT_CONST / f * 98 / 100;
  1471. tmp = be32toh(tmp);
  1472. memcpy(send_pkg.data + AVA7_DEFAULT_PLL_CNT * 4 + 4, &tmp, 4);
  1473. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set freq miner %x-%x",
  1474. avalon7->drv->name, avalon7->device_id, addr,
  1475. miner_id, be32toh(tmp));
  1476. /* Package the data */
  1477. avalon7_init_pkg(&send_pkg, AVA7_P_SET_PLL, miner_id + 1, info->miner_count[addr]);
  1478. if (addr == AVA7_MODULE_BROADCAST)
  1479. avalon7_send_bc_pkgs(avalon7, &send_pkg);
  1480. else
  1481. avalon7_iic_xfer_pkg(avalon7, addr, &send_pkg, NULL);
  1482. }
  1483. static void avalon7_set_factory_info(struct cgpu_info *avalon7, int addr, uint8_t value[])
  1484. {
  1485. struct avalon7_pkg send_pkg;
  1486. uint8_t i;
  1487. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1488. for (i = 0; i < AVA7_DEFAULT_FACTORY_INFO_CNT; i++)
  1489. send_pkg.data[i] = value[i];
  1490. /* Package the data */
  1491. avalon7_init_pkg(&send_pkg, AVA7_P_SET_FAC, 1, 1);
  1492. if (addr == AVA7_MODULE_BROADCAST)
  1493. avalon7_send_bc_pkgs(avalon7, &send_pkg);
  1494. else
  1495. avalon7_iic_xfer_pkg(avalon7, addr, &send_pkg, NULL);
  1496. }
  1497. static void avalon7_set_ss_param(struct cgpu_info *avalon7, int addr)
  1498. {
  1499. struct avalon7_pkg send_pkg;
  1500. uint32_t tmp;
  1501. if (!opt_avalon7_smart_speed)
  1502. return;
  1503. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1504. tmp = be32toh(opt_avalon7_th_pass);
  1505. memcpy(send_pkg.data, &tmp, 4);
  1506. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set th pass %u",
  1507. avalon7->drv->name, avalon7->device_id, addr,
  1508. opt_avalon7_th_pass);
  1509. tmp = be32toh(opt_avalon7_th_fail);
  1510. memcpy(send_pkg.data + 4, &tmp, 4);
  1511. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set th fail %u",
  1512. avalon7->drv->name, avalon7->device_id, addr,
  1513. opt_avalon7_th_fail);
  1514. tmp = be32toh(opt_avalon7_th_init);
  1515. memcpy(send_pkg.data + 8, &tmp, 4);
  1516. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set th init %u",
  1517. avalon7->drv->name, avalon7->device_id, addr,
  1518. opt_avalon7_th_init);
  1519. tmp = be32toh(opt_avalon7_th_ms);
  1520. memcpy(send_pkg.data + 12, &tmp, 4);
  1521. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set th ms %u",
  1522. avalon7->drv->name, avalon7->device_id, addr,
  1523. opt_avalon7_th_ms);
  1524. tmp = be32toh(opt_avalon7_th_timeout);
  1525. memcpy(send_pkg.data + 16, &tmp, 4);
  1526. applog(LOG_DEBUG, "%s-%d-%d: avalon7 set th timeout %u",
  1527. avalon7->drv->name, avalon7->device_id, addr,
  1528. opt_avalon7_th_timeout);
  1529. /* Package the data */
  1530. avalon7_init_pkg(&send_pkg, AVA7_P_SET_SS, 1, 1);
  1531. if (addr == AVA7_MODULE_BROADCAST)
  1532. avalon7_send_bc_pkgs(avalon7, &send_pkg);
  1533. else
  1534. avalon7_iic_xfer_pkg(avalon7, addr, &send_pkg, NULL);
  1535. }
  1536. static void avalon7_stratum_finish(struct cgpu_info *avalon7)
  1537. {
  1538. struct avalon7_pkg send_pkg;
  1539. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1540. avalon7_init_pkg(&send_pkg, AVA7_P_JOB_FIN, 1, 1);
  1541. avalon7_send_bc_pkgs(avalon7, &send_pkg);
  1542. }
  1543. static void avalon7_set_finish(struct cgpu_info *avalon7, int addr)
  1544. {
  1545. struct avalon7_pkg send_pkg;
  1546. memset(send_pkg.data, 0, AVA7_P_DATA_LEN);
  1547. avalon7_init_pkg(&send_pkg, AVA7_P_SET_FIN, 1, 1);
  1548. avalon7_iic_xfer_pkg(avalon7, addr, &send_pkg, NULL);
  1549. }
  1550. static void avalon7_sswork_update(struct cgpu_info *avalon7)
  1551. {
  1552. struct avalon7_info *info = avalon7->device_data;
  1553. struct thr_info *thr = avalon7->thr[0];
  1554. struct pool *pool;
  1555. int coinbase_len_posthash, coinbase_len_prehash;
  1556. /*
  1557. * NOTE: We need mark work_restart to private information,
  1558. * So that it cann't reset by hash_driver_work
  1559. */
  1560. if (thr->work_restart)
  1561. info->work_restart = thr->work_restart;
  1562. applog(LOG_DEBUG, "%s-%d: New stratum: restart: %d, update: %d",
  1563. avalon7->drv->name, avalon7->device_id,
  1564. thr->work_restart, thr->work_update);
  1565. /* Step 1: MM protocol check */
  1566. pool = current_pool();
  1567. if (!pool->has_stratum)
  1568. quit(1, "%s-%d: MM has to use stratum pools", avalon7->drv->name, avalon7->device_id);
  1569. coinbase_len_prehash = pool->nonce2_offset - (pool->nonce2_offset % SHA256_BLOCK_SIZE);
  1570. coinbase_len_posthash = pool->coinbase_len - coinbase_len_prehash;
  1571. if (coinbase_len_posthash + SHA256_BLOCK_SIZE > AVA7_P_COINBASE_SIZE) {
  1572. applog(LOG_ERR, "%s-%d: MM pool modified coinbase length(%d) is more than %d",
  1573. avalon7->drv->name, avalon7->device_id,
  1574. coinbase_len_posthash + SHA256_BLOCK_SIZE, AVA7_P_COINBASE_SIZE);
  1575. return;
  1576. }
  1577. if (pool->merkles > AVA7_P_MERKLES_COUNT) {
  1578. applog(LOG_ERR, "%s-%d: MM merkles has to be less then %d", avalon7->drv->name, avalon7->device_id, AVA7_P_MERKLES_COUNT);
  1579. return;
  1580. }
  1581. if (pool->n2size < 3) {
  1582. applog(LOG_ERR, "%s-%d: MM nonce2 size has to be >= 3 (%d)", avalon7->drv->name, avalon7->device_id, pool->n2size);
  1583. return;
  1584. }
  1585. cg_wlock(&info->update_lock);
  1586. /* Step 2: Send out stratum pkgs */
  1587. cg_rlock(&pool->data_lock);
  1588. cgtime(&info->last_stratum);
  1589. info->pool_no = pool->pool_no;
  1590. copy_pool_stratum(&info->pool2, &info->pool1);
  1591. copy_pool_stratum(&info->pool1, &info->pool0);
  1592. copy_pool_stratum(&info->pool0, pool);
  1593. avalon7_stratum_pkgs(avalon7, pool);
  1594. cg_runlock(&pool->data_lock);
  1595. /* Step 3: Send out finish pkg */
  1596. avalon7_stratum_finish(avalon7);
  1597. cg_wunlock(&info->update_lock);
  1598. }
  1599. static int64_t avalon7_scanhash(struct thr_info *thr)
  1600. {
  1601. struct cgpu_info *avalon7 = thr->cgpu;
  1602. struct avalon7_info *info = avalon7->device_data;
  1603. struct timeval current;
  1604. int i, j, k, count = 0;
  1605. int temp_max;
  1606. int64_t ret;
  1607. bool update_settings = false;
  1608. if ((info->connecter == AVA7_CONNECTER_AUC) &&
  1609. (unlikely(avalon7->usbinfo.nodev))) {
  1610. applog(LOG_ERR, "%s-%d: Device disappeared, shutting down thread",
  1611. avalon7->drv->name, avalon7->device_id);
  1612. return -1;
  1613. }
  1614. /* Step 1: Stop polling and detach the device if there is no stratum in 3 minutes, network is down */
  1615. cgtime(&current);
  1616. if (tdiff(&current, &(info->last_stratum)) > 180.0) {
  1617. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  1618. if (!info->enable[i])
  1619. continue;
  1620. detach_module(avalon7, i);
  1621. }
  1622. info->mm_count = 0;
  1623. return 0;
  1624. }
  1625. /* Step 2: Try to detect new modules */
  1626. if ((tdiff(&current, &(info->last_detect)) > AVA7_MODULE_DETECT_INTERVAL) ||
  1627. !info->mm_count) {
  1628. cgtime(&info->last_detect);
  1629. detect_modules(avalon7);
  1630. }
  1631. /* Step 3: ASIC configrations (voltage and frequency) */
  1632. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  1633. if (!info->enable[i])
  1634. continue;
  1635. update_settings = false;
  1636. /* Check temperautre */
  1637. temp_max = get_temp_max(info, i);
  1638. /* Enter too hot */
  1639. if (temp_max >= info->temp_overheat[i])
  1640. info->cutoff[i] = 1;
  1641. /* Exit too hot */
  1642. if (info->cutoff[i] && (temp_max <= (info->temp_overheat[i] - 10)))
  1643. info->cutoff[i] = 0;
  1644. switch (info->freq_mode[i]) {
  1645. case AVA7_FREQ_INIT_MODE:
  1646. update_settings = true;
  1647. /* Make sure to send configuration first */
  1648. thr->work_update = false;
  1649. for (j = 0; j < info->miner_count[i]; j++) {
  1650. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++)
  1651. info->set_frequency[i][j][k] = opt_avalon7_freq[k];
  1652. }
  1653. avalon7_init_setting(avalon7, i);
  1654. info->freq_mode[i] = AVA7_FREQ_PLLADJ_MODE;
  1655. break;
  1656. case AVA7_FREQ_PLLADJ_MODE:
  1657. if (opt_avalon7_smart_speed == AVA7_DEFAULT_SMARTSPEED_OFF)
  1658. break;
  1659. /* AVA7_DEFAULT_SMARTSPEED_MODE1: auto speed by A3212 chips */
  1660. break;
  1661. default:
  1662. applog(LOG_ERR, "%s-%d-%d: Invalid frequency mode %d",
  1663. avalon7->drv->name, avalon7->device_id, i, info->freq_mode[i]);
  1664. break;
  1665. }
  1666. if (update_settings) {
  1667. cg_wlock(&info->update_lock);
  1668. avalon7_set_voltage(avalon7, i, info->set_voltage[i]);
  1669. for (j = 0; j < info->miner_count[i]; j++)
  1670. avalon7_set_freq(avalon7, i, j, info->set_frequency[i][j]);
  1671. if (opt_avalon7_smart_speed)
  1672. avalon7_set_ss_param(avalon7, i);
  1673. avalon7_set_finish(avalon7, i);
  1674. cg_wunlock(&info->update_lock);
  1675. }
  1676. }
  1677. /* Step 4: Polling */
  1678. cg_rlock(&info->update_lock);
  1679. polling(avalon7);
  1680. cg_runlock(&info->update_lock);
  1681. /* Step 5: Calculate mm count */
  1682. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  1683. if (info->enable[i])
  1684. count++;
  1685. }
  1686. info->mm_count = count;
  1687. /* Step 6: Calculate hashes. Use the diff1 value which is scaled by
  1688. * device diff and is usually lower than pool diff which will give a
  1689. * more stable result, but remove diff rejected shares to more closely
  1690. * approximate diff accepted values. */
  1691. info->pending_diff1 += avalon7->diff1 - info->last_diff1;
  1692. info->last_diff1 = avalon7->diff1;
  1693. info->pending_diff1 -= avalon7->diff_rejected - info->last_rej;
  1694. info->last_rej = avalon7->diff_rejected;
  1695. if (info->pending_diff1 && !info->firsthash.tv_sec) {
  1696. cgtime(&info->firsthash);
  1697. copy_time(&(avalon7->dev_start_tv), &(info->firsthash));
  1698. }
  1699. if (info->pending_diff1 <= 0)
  1700. ret = 0;
  1701. else {
  1702. ret = info->pending_diff1;
  1703. info->pending_diff1 = 0;
  1704. }
  1705. return ret * 0xffffffffull;
  1706. }
  1707. static float avalon7_hash_cal(struct cgpu_info *avalon7, int modular_id)
  1708. {
  1709. struct avalon7_info *info = avalon7->device_data;
  1710. uint32_t tmp_freq[AVA7_DEFAULT_PLL_CNT];
  1711. unsigned int i, j;
  1712. float mhsmm;
  1713. mhsmm = 0;
  1714. for (i = 0; i < info->miner_count[modular_id]; i++) {
  1715. for (j = 0; j < AVA7_DEFAULT_PLL_CNT; j++)
  1716. tmp_freq[j] = info->set_frequency[modular_id][i][j];
  1717. for (j = 0; j < AVA7_DEFAULT_PLL_CNT; j++)
  1718. mhsmm += (info->get_pll[modular_id][i][j] * tmp_freq[j]);
  1719. }
  1720. return mhsmm;
  1721. }
  1722. #define STATBUFLEN_WITHOUT_DBG (6 * 1024)
  1723. #define STATBUFLEN_WITH_DBG (6 * 7 * 1024)
  1724. static struct api_data *avalon7_api_stats(struct cgpu_info *avalon7)
  1725. {
  1726. struct api_data *root = NULL;
  1727. struct avalon7_info *info = avalon7->device_data;
  1728. int i, j, k;
  1729. double a, b, dh;
  1730. char buf[256];
  1731. char *statbuf = NULL;
  1732. struct timeval current;
  1733. float mhsmm, auc_temp = 0.0;
  1734. cgtime(&current);
  1735. if (opt_debug)
  1736. statbuf = cgcalloc(STATBUFLEN_WITH_DBG, 1);
  1737. else
  1738. statbuf = cgcalloc(STATBUFLEN_WITHOUT_DBG, 1);
  1739. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  1740. if (!info->enable[i])
  1741. continue;
  1742. sprintf(buf, "Ver[%s]", info->mm_version[i]);
  1743. strcpy(statbuf, buf);
  1744. sprintf(buf, " DNA[%02x%02x%02x%02x%02x%02x%02x%02x]",
  1745. info->mm_dna[i][0],
  1746. info->mm_dna[i][1],
  1747. info->mm_dna[i][2],
  1748. info->mm_dna[i][3],
  1749. info->mm_dna[i][4],
  1750. info->mm_dna[i][5],
  1751. info->mm_dna[i][6],
  1752. info->mm_dna[i][7]);
  1753. strcat(statbuf, buf);
  1754. sprintf(buf, " Elapsed[%.0f]", tdiff(&current, &(info->elapsed[i])));
  1755. strcat(statbuf, buf);
  1756. strcat(statbuf, " MW[");
  1757. info->local_works[i] = 0;
  1758. for (j = 0; j < info->miner_count[i]; j++) {
  1759. info->local_works[i] += info->local_works_i[i][j];
  1760. sprintf(buf, "%"PRIu64" ", info->local_works_i[i][j]);
  1761. strcat(statbuf, buf);
  1762. }
  1763. statbuf[strlen(statbuf) - 1] = ']';
  1764. sprintf(buf, " LW[%"PRIu64"]", info->local_works[i]);
  1765. strcat(statbuf, buf);
  1766. strcat(statbuf, " MH[");
  1767. info->hw_works[i] = 0;
  1768. for (j = 0; j < info->miner_count[i]; j++) {
  1769. info->hw_works[i] += info->hw_works_i[i][j];
  1770. sprintf(buf, "%"PRIu64" ", info->hw_works_i[i][j]);
  1771. strcat(statbuf, buf);
  1772. }
  1773. statbuf[strlen(statbuf) - 1] = ']';
  1774. sprintf(buf, " HW[%"PRIu64"]", info->hw_works[i]);
  1775. strcat(statbuf, buf);
  1776. a = 0;
  1777. b = 0;
  1778. for (j = 0; j < info->miner_count[i]; j++) {
  1779. for (k = 0; k < info->asic_count[i]; k++) {
  1780. a += info->get_asic[i][j][k][0];
  1781. b += info->get_asic[i][j][k][1];
  1782. }
  1783. }
  1784. dh = b ? (b / (a + b)) * 100: 0;
  1785. sprintf(buf, " DH[%.3f%%]", dh);
  1786. strcat(statbuf, buf);
  1787. sprintf(buf, " Temp[%d]", info->temp_mm[i]);
  1788. strcat(statbuf, buf);
  1789. sprintf(buf, " TMax[%d]", get_temp_max(info, i));
  1790. strcat(statbuf, buf);
  1791. sprintf(buf, " Fan[%d]", info->fan_cpm[i]);
  1792. strcat(statbuf, buf);
  1793. sprintf(buf, " FanR[%d%%]", info->fan_pct[i]);
  1794. strcat(statbuf, buf);
  1795. sprintf(buf, " Vi[");
  1796. strcat(statbuf, buf);
  1797. for (j = 0; j < info->miner_count[i]; j++) {
  1798. sprintf(buf, "%d ", info->get_vin[i][j]);
  1799. strcat(statbuf, buf);
  1800. }
  1801. statbuf[strlen(statbuf) - 1] = ']';
  1802. sprintf(buf, " Vo[");
  1803. strcat(statbuf, buf);
  1804. for (j = 0; j < info->miner_count[i]; j++) {
  1805. sprintf(buf, "%d ", info->get_voltage[i][j]);
  1806. strcat(statbuf, buf);
  1807. }
  1808. statbuf[strlen(statbuf) - 1] = ']';
  1809. if (opt_debug) {
  1810. for (j = 0; j < info->miner_count[i]; j++) {
  1811. sprintf(buf, " PLL%d[", j);
  1812. strcat(statbuf, buf);
  1813. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++) {
  1814. sprintf(buf, "%d ", info->get_pll[i][j][k]);
  1815. strcat(statbuf, buf);
  1816. }
  1817. statbuf[strlen(statbuf) - 1] = ']';
  1818. }
  1819. }
  1820. mhsmm = avalon7_hash_cal(avalon7, i);
  1821. sprintf(buf, " GHSmm[%.2f] WU[%.2f] Freq[%.2f]", (float)mhsmm / 1000,
  1822. info->diff1[i] / tdiff(&current, &(info->elapsed[i])) * 60.0,
  1823. (float)mhsmm / (info->asic_count[i] * info->miner_count[i] * 128));
  1824. strcat(statbuf, buf);
  1825. sprintf(buf, " PG[%d]", info->power_good[i]);
  1826. strcat(statbuf, buf);
  1827. sprintf(buf, " Led[%d]", info->led_indicator[i]);
  1828. strcat(statbuf, buf);
  1829. for (j = 0; j < info->miner_count[i]; j++) {
  1830. sprintf(buf, " MW%d[", j);
  1831. strcat(statbuf, buf);
  1832. for (k = 0; k < info->asic_count[i]; k++) {
  1833. sprintf(buf, "%"PRIu64" ", info->chip_matching_work[i][j][k]);
  1834. strcat(statbuf, buf);
  1835. }
  1836. statbuf[strlen(statbuf) - 1] = ']';
  1837. }
  1838. sprintf(buf, " TA[%d]", info->total_asics[i]);
  1839. strcat(statbuf, buf);
  1840. strcat(statbuf, " ECHU[");
  1841. for (j = 0; j < info->miner_count[i]; j++) {
  1842. sprintf(buf, "%d ", info->error_code[i][j]);
  1843. strcat(statbuf, buf);
  1844. }
  1845. statbuf[strlen(statbuf) - 1] = ']';
  1846. sprintf(buf, " ECMM[%d]", info->error_code[i][j]);
  1847. strcat(statbuf, buf);
  1848. if (opt_debug) {
  1849. sprintf(buf, " FAC0[%d]", info->factory_info[0]);
  1850. strcat(statbuf, buf);
  1851. for (j = 0; j < info->miner_count[i]; j++) {
  1852. sprintf(buf, " SF%d[", j);
  1853. strcat(statbuf, buf);
  1854. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++) {
  1855. sprintf(buf, "%d ", info->set_frequency[i][j][k]);
  1856. strcat(statbuf, buf);
  1857. }
  1858. statbuf[strlen(statbuf) - 1] = ']';
  1859. }
  1860. strcat(statbuf, " PMUV[");
  1861. for (j = 0; j < AVA7_DEFAULT_PMU_CNT; j++) {
  1862. sprintf(buf, "%s ", info->pmu_version[i][j]);
  1863. strcat(statbuf, buf);
  1864. }
  1865. statbuf[strlen(statbuf) - 1] = ']';
  1866. for (j = 0; j < info->miner_count[i]; j++) {
  1867. sprintf(buf, " ERATIO%d[", j);
  1868. strcat(statbuf, buf);
  1869. for (k = 0; k < info->asic_count[i]; k++) {
  1870. if (info->get_asic[i][j][k][0])
  1871. sprintf(buf, "%.2f%% ", (double)(info->get_asic[i][j][k][1] * 100.0 / (info->get_asic[i][j][k][0] + info->get_asic[i][j][k][1])));
  1872. else
  1873. sprintf(buf, "%.2f%% ", 0.0);
  1874. strcat(statbuf, buf);
  1875. }
  1876. statbuf[strlen(statbuf) - 1] = ']';
  1877. }
  1878. int l;
  1879. /* i: modular, j: miner, k:asic, l:value */
  1880. for (l = 0; l < 5; l++) {
  1881. for (j = 0; j < info->miner_count[i]; j++) {
  1882. sprintf(buf, " C_%d_%02d[", j, l);
  1883. strcat(statbuf, buf);
  1884. for (k = 0; k < info->asic_count[i]; k++) {
  1885. sprintf(buf, "%5d ", info->get_asic[i][j][k][l]);
  1886. strcat(statbuf, buf);
  1887. }
  1888. statbuf[strlen(statbuf) - 1] = ']';
  1889. }
  1890. }
  1891. for (j = 0; j < info->miner_count[i]; j++) {
  1892. sprintf(buf, " GHSmm%02d[", j);
  1893. strcat(statbuf, buf);
  1894. for (k = 0; k < info->asic_count[i]; k++) {
  1895. mhsmm = 0;
  1896. for (l = 5; l < 11; l++)
  1897. mhsmm += (info->get_asic[i][j][k][l] * info->set_frequency[i][j][l - 5]);
  1898. sprintf(buf, "%.2f ", mhsmm / 1000);
  1899. strcat(statbuf, buf);
  1900. }
  1901. statbuf[strlen(statbuf) - 1] = ']';
  1902. }
  1903. }
  1904. sprintf(buf, " FM[%d]", info->freq_mode[i]);
  1905. strcat(statbuf, buf);
  1906. strcat(statbuf, " CRC[");
  1907. for (j = 0; j < info->miner_count[i]; j++) {
  1908. sprintf(buf, "%d ", info->error_crc[i][j]);
  1909. strcat(statbuf, buf);
  1910. }
  1911. statbuf[strlen(statbuf) - 1] = ']';
  1912. strcat(statbuf, " PVT_T[");
  1913. for (j = 0; j < info->miner_count[i]; j++) {
  1914. sprintf(buf, "%d-%d/%d-%d/%d ",
  1915. info->temp[i][j][0],
  1916. info->temp[i][j][2],
  1917. info->temp[i][j][1],
  1918. info->temp[i][j][3],
  1919. info->temp[i][j][4]);
  1920. strcat(statbuf, buf);
  1921. }
  1922. statbuf[strlen(statbuf) - 1] = ']';
  1923. statbuf[strlen(statbuf)] = '\0';
  1924. sprintf(buf, "MM ID%d", i);
  1925. root = api_add_string(root, buf, statbuf, true);
  1926. }
  1927. free(statbuf);
  1928. root = api_add_int(root, "MM Count", &(info->mm_count), true);
  1929. root = api_add_int(root, "Smart Speed", &opt_avalon7_smart_speed, true);
  1930. if (info->connecter == AVA7_CONNECTER_IIC)
  1931. root = api_add_string(root, "Connecter", "IIC", true);
  1932. if (info->connecter == AVA7_CONNECTER_AUC) {
  1933. root = api_add_string(root, "Connecter", "AUC", true);
  1934. root = api_add_string(root, "AUC VER", info->auc_version, false);
  1935. root = api_add_int(root, "AUC I2C Speed", &(info->auc_speed), true);
  1936. root = api_add_int(root, "AUC I2C XDelay", &(info->auc_xdelay), true);
  1937. root = api_add_int(root, "AUC Sensor", &(info->auc_sensor), true);
  1938. auc_temp = decode_auc_temp(info->auc_sensor);
  1939. root = api_add_temp(root, "AUC Temperature", &auc_temp, true);
  1940. }
  1941. root = api_add_bool(root, "Connection Overloaded", &info->conn_overloaded, true);
  1942. root = api_add_int(root, "Voltage Offset", &opt_avalon7_voltage_offset, true);
  1943. root = api_add_uint32(root, "Nonce Mask", &opt_avalon7_nonce_mask, true);
  1944. return root;
  1945. }
  1946. /* format: voltage[-addr[-miner]]
  1947. * add4[0, AVA7_DEFAULT_MODULARS - 1], 0 means all modulars
  1948. * miner[0, miner_count], 0 means all miners
  1949. */
  1950. char *set_avalon7_device_voltage(struct cgpu_info *avalon7, char *arg)
  1951. {
  1952. struct avalon7_info *info = avalon7->device_data;
  1953. unsigned int val, addr = 0, i, j;
  1954. uint32_t miner_id = 0;
  1955. if (!(*arg))
  1956. return NULL;
  1957. sscanf(arg, "%d-%d-%d", &val, &addr, &miner_id);
  1958. if (!val)
  1959. val = AVA7_DEFAULT_VOLTAGE_MIN;
  1960. if (val < AVA7_DEFAULT_VOLTAGE_MIN || val > AVA7_DEFAULT_VOLTAGE_MAX)
  1961. return "Invalid value passed to set_avalon7_device_voltage";
  1962. if (addr >= AVA7_DEFAULT_MODULARS) {
  1963. applog(LOG_ERR, "invalid modular index: %d, valid range 0-%d", addr, (AVA7_DEFAULT_MODULARS - 1));
  1964. return "Invalid modular index to set_avalon7_device_voltage";
  1965. }
  1966. if (!info->enable[addr]) {
  1967. applog(LOG_ERR, "Disabled modular:%d", addr);
  1968. return "Disabled modular to set_avalon7_device_voltage";
  1969. }
  1970. if (miner_id > info->miner_count[addr]) {
  1971. applog(LOG_ERR, "invalid miner index: %d, valid range 0-%d", miner_id, info->miner_count[addr]);
  1972. return "Invalid miner index to set_avalon7_device_voltage";
  1973. }
  1974. if (!addr) {
  1975. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  1976. if (!info->enable[i])
  1977. continue;
  1978. if (miner_id)
  1979. info->set_voltage[i][miner_id - 1] = val;
  1980. else {
  1981. for (j = 0; j < info->miner_count[i]; j++)
  1982. info->set_voltage[i][j] = val;
  1983. }
  1984. avalon7_set_voltage(avalon7, i, info->set_voltage[i]);
  1985. }
  1986. } else {
  1987. if (miner_id)
  1988. info->set_voltage[addr][miner_id - 1] = val;
  1989. else {
  1990. for (j = 0; j < info->miner_count[addr]; j++)
  1991. info->set_voltage[addr][j] = val;
  1992. }
  1993. avalon7_set_voltage(avalon7, addr, info->set_voltage[addr]);
  1994. }
  1995. applog(LOG_NOTICE, "%s-%d: Update voltage to %d",
  1996. avalon7->drv->name, avalon7->device_id, val);
  1997. return NULL;
  1998. }
  1999. /* format: freq[-addr[-miner]]
  2000. * add4[0, AVA7_DEFAULT_MODULARS - 1], 0 means all modulars
  2001. * miner[0, miner_count], 0 means all miners
  2002. */
  2003. char *set_avalon7_device_freq(struct cgpu_info *avalon7, char *arg)
  2004. {
  2005. struct avalon7_info *info = avalon7->device_data;
  2006. unsigned int val, addr = 0, i, j, k;
  2007. uint32_t miner_id = 0;
  2008. if (!(*arg))
  2009. return NULL;
  2010. sscanf(arg, "%d-%d-%d", &val, &addr, &miner_id);
  2011. if (!val)
  2012. val = AVA7_DEFAULT_FREQUENCY_MIN;
  2013. if (val < AVA7_DEFAULT_FREQUENCY_MIN || val > AVA7_DEFAULT_FREQUENCY_MAX)
  2014. return "Invalid value passed to set_avalon7_device_freq";
  2015. if (addr >= AVA7_DEFAULT_MODULARS) {
  2016. applog(LOG_ERR, "invalid modular index: %d, valid range 0-%d", addr, (AVA7_DEFAULT_MODULARS - 1));
  2017. return "Invalid modular index to set_avalon7_device_freq";
  2018. }
  2019. if (!info->enable[addr]) {
  2020. applog(LOG_ERR, "Disabled modular:%d", addr);
  2021. return "Disabled modular to set_avalon7_device_freq";
  2022. }
  2023. if (miner_id > info->miner_count[addr]) {
  2024. applog(LOG_ERR, "invalid miner index: %d, valid range 0-%d", miner_id, info->miner_count[addr]);
  2025. return "Invalid miner index to set_avalon7_device_freq";
  2026. }
  2027. if (!addr) {
  2028. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  2029. if (!info->enable[i])
  2030. continue;
  2031. if (miner_id) {
  2032. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++)
  2033. info->set_frequency[i][miner_id - 1][k] = val;
  2034. avalon7_set_freq(avalon7, i, miner_id, info->set_frequency[i][miner_id]);
  2035. } else {
  2036. for (j = 0; j < info->miner_count[i]; j++) {
  2037. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++)
  2038. info->set_frequency[i][j][k] = val;
  2039. avalon7_set_freq(avalon7, i, j, info->set_frequency[i][j]);
  2040. }
  2041. }
  2042. }
  2043. } else {
  2044. if (miner_id) {
  2045. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++)
  2046. info->set_frequency[addr][miner_id - 1][k] = val;
  2047. avalon7_set_freq(avalon7, addr, miner_id, info->set_frequency[addr][miner_id]);
  2048. } else {
  2049. for (j = 0; j < info->miner_count[addr]; j++) {
  2050. for (k = 0; k < AVA7_DEFAULT_PLL_CNT; k++)
  2051. info->set_frequency[addr][j][k] = val;
  2052. avalon7_set_freq(avalon7, addr, j, info->set_frequency[addr][j]);
  2053. }
  2054. }
  2055. }
  2056. applog(LOG_NOTICE, "%s-%d: Update frequency to %d",
  2057. avalon7->drv->name, avalon7->device_id, val);
  2058. return NULL;
  2059. }
  2060. char *set_avalon7_factory_info(struct cgpu_info *avalon7, char *arg)
  2061. {
  2062. struct avalon7_info *info = avalon7->device_data;
  2063. int val;
  2064. if (!(*arg))
  2065. return NULL;
  2066. sscanf(arg, "%d", &val);
  2067. if (!val)
  2068. val = AVA7_DEFAULT_FACTORY_INFO_0;
  2069. if (val < AVA7_DEFAULT_FACTORY_INFO_0_MIN || val > AVA7_DEFAULT_FACTORY_INFO_0_MAX)
  2070. return "Invalid value passed to set_avalon7_factory_info";
  2071. info->factory_info[0] = val;
  2072. avalon7_set_factory_info(avalon7, 0, (uint8_t *)info->factory_info);
  2073. applog(LOG_NOTICE, "%s-%d: Update factory info %d",
  2074. avalon7->drv->name, avalon7->device_id, val);
  2075. return NULL;
  2076. }
  2077. static char *avalon7_set_device(struct cgpu_info *avalon7, char *option, char *setting, char *replybuf)
  2078. {
  2079. unsigned int val;
  2080. struct avalon7_info *info = avalon7->device_data;
  2081. if (strcasecmp(option, "help") == 0) {
  2082. sprintf(replybuf, "pdelay|fan|frequency|led|voltage");
  2083. return replybuf;
  2084. }
  2085. if (strcasecmp(option, "pdelay") == 0) {
  2086. if (!setting || !*setting) {
  2087. sprintf(replybuf, "missing polling delay setting");
  2088. return replybuf;
  2089. }
  2090. val = (unsigned int)atoi(setting);
  2091. if (val < 1 || val > 65535) {
  2092. sprintf(replybuf, "invalid polling delay: %d, valid range 1-65535", val);
  2093. return replybuf;
  2094. }
  2095. opt_avalon7_polling_delay = val;
  2096. applog(LOG_NOTICE, "%s-%d: Update polling delay to: %d",
  2097. avalon7->drv->name, avalon7->device_id, val);
  2098. return NULL;
  2099. }
  2100. if (strcasecmp(option, "fan") == 0) {
  2101. if (!setting || !*setting) {
  2102. sprintf(replybuf, "missing fan value");
  2103. return replybuf;
  2104. }
  2105. if (set_avalon7_fan(setting)) {
  2106. sprintf(replybuf, "invalid fan value, valid range 0-100");
  2107. return replybuf;
  2108. }
  2109. applog(LOG_NOTICE, "%s-%d: Update fan to %d-%d",
  2110. avalon7->drv->name, avalon7->device_id,
  2111. opt_avalon7_fan_min, opt_avalon7_fan_max);
  2112. return NULL;
  2113. }
  2114. if (strcasecmp(option, "frequency") == 0) {
  2115. if (!setting || !*setting) {
  2116. sprintf(replybuf, "missing frequency value");
  2117. return replybuf;
  2118. }
  2119. return set_avalon7_device_freq(avalon7, setting);
  2120. }
  2121. if (strcasecmp(option, "led") == 0) {
  2122. int val_led = -1;
  2123. if (!setting || !*setting) {
  2124. sprintf(replybuf, "missing module_id setting");
  2125. return replybuf;
  2126. }
  2127. sscanf(setting, "%d-%d", &val, &val_led);
  2128. if (val < 1 || val >= AVA7_DEFAULT_MODULARS) {
  2129. sprintf(replybuf, "invalid module_id: %d, valid range 1-%d", val, AVA7_DEFAULT_MODULARS);
  2130. return replybuf;
  2131. }
  2132. if (!info->enable[val]) {
  2133. sprintf(replybuf, "the current module was disabled %d", val);
  2134. return replybuf;
  2135. }
  2136. if (val_led == -1)
  2137. info->led_indicator[val] = !info->led_indicator[val];
  2138. else {
  2139. if (val_led < 0 || val_led > 1) {
  2140. sprintf(replybuf, "invalid LED status: %d, valid value 0|1", val_led);
  2141. return replybuf;
  2142. }
  2143. if (val_led != info->led_indicator[val])
  2144. info->led_indicator[val] = val_led;
  2145. }
  2146. applog(LOG_NOTICE, "%s-%d: Module:%d, LED: %s",
  2147. avalon7->drv->name, avalon7->device_id,
  2148. val, info->led_indicator[val] ? "on" : "off");
  2149. return NULL;
  2150. }
  2151. if (strcasecmp(option, "voltage") == 0) {
  2152. if (!setting || !*setting) {
  2153. sprintf(replybuf, "missing voltage value");
  2154. return replybuf;
  2155. }
  2156. return set_avalon7_device_voltage(avalon7, setting);
  2157. }
  2158. if (strcasecmp(option, "factory") == 0) {
  2159. if (!setting || !*setting) {
  2160. sprintf(replybuf, "missing factory info");
  2161. return replybuf;
  2162. }
  2163. return set_avalon7_factory_info(avalon7, setting);
  2164. }
  2165. if (strcasecmp(option, "reboot") == 0) {
  2166. if (!setting || !*setting) {
  2167. sprintf(replybuf, "missing reboot value");
  2168. return replybuf;
  2169. }
  2170. sscanf(setting, "%d", &val);
  2171. if (val < 1 || val >= AVA7_DEFAULT_MODULARS) {
  2172. sprintf(replybuf, "invalid module_id: %d, valid range 1-%d", val, AVA7_DEFAULT_MODULARS);
  2173. return replybuf;
  2174. }
  2175. info->reboot[val] = true;
  2176. return NULL;
  2177. }
  2178. sprintf(replybuf, "Unknown option: %s", option);
  2179. return replybuf;
  2180. }
  2181. static void avalon7_statline_before(char *buf, size_t bufsiz, struct cgpu_info *avalon7)
  2182. {
  2183. struct avalon7_info *info = avalon7->device_data;
  2184. int temp = -273;
  2185. int fanmin = AVA7_DEFAULT_FAN_MAX;
  2186. int i, j, k;
  2187. uint32_t frequency = 0;
  2188. float ghs_sum = 0, mhsmm = 0;
  2189. double pass_num = 0.0, fail_num = 0.0;
  2190. for (i = 1; i < AVA7_DEFAULT_MODULARS; i++) {
  2191. if (!info->enable[i])
  2192. continue;
  2193. if (fanmin >= info->fan_pct[i])
  2194. fanmin = info->fan_pct[i];
  2195. if (temp < get_temp_max(info, i))
  2196. temp = get_temp_max(info, i);
  2197. mhsmm = avalon7_hash_cal(avalon7, i);
  2198. frequency += (mhsmm / (info->asic_count[i] * info->miner_count[i] * 128));
  2199. ghs_sum += (mhsmm / 1000);
  2200. for (j = 0; j < info->miner_count[i]; j++) {
  2201. for (k = 0; k < info->asic_count[i]; k++) {
  2202. pass_num += info->get_asic[i][j][k][0];
  2203. fail_num += info->get_asic[i][j][k][1];
  2204. }
  2205. }
  2206. }
  2207. if (info->mm_count)
  2208. frequency /= info->mm_count;
  2209. tailsprintf(buf, bufsiz, "%4dMhz %.2fGHS %2dC %.2f%% %3d%%", frequency,
  2210. ghs_sum, temp, (fail_num + pass_num) ? fail_num * 100.0 / (fail_num + pass_num) : 0, fanmin);
  2211. }
  2212. struct device_drv avalon7_drv = {
  2213. .drv_id = DRIVER_avalon7,
  2214. .dname = "avalon7",
  2215. .name = "AV7",
  2216. .set_device = avalon7_set_device,
  2217. .get_api_stats = avalon7_api_stats,
  2218. .get_statline_before = avalon7_statline_before,
  2219. .drv_detect = avalon7_detect,
  2220. .thread_prepare = avalon7_prepare,
  2221. .hash_work = hash_driver_work,
  2222. .flush_work = avalon7_sswork_update,
  2223. .update_work = avalon7_sswork_update,
  2224. .scanwork = avalon7_scanhash,
  2225. .max_diff = AVA7_DRV_DIFFMAX,
  2226. .genwork = true,
  2227. };