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@@ -0,0 +1,498 @@
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+--- a/drivers/net/ethernet/atheros/alx/ethtool.c
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++++ b/drivers/net/ethernet/atheros/alx/ethtool.c
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+@@ -321,11 +321,47 @@ static int alx_get_sset_count(struct net_device *netdev, int sset)
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+ }
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+ }
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+
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++static void alx_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
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++{
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++ struct alx_priv *alx = netdev_priv(netdev);
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++ struct alx_hw *hw = &alx->hw;
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++
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++ wol->supported = WAKE_MAGIC | WAKE_PHY;
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++ wol->wolopts = 0;
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++
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++ if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
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++ wol->wolopts |= WAKE_MAGIC;
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++ if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY)
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++ wol->wolopts |= WAKE_PHY;
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++}
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++
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++static int alx_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
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++{
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++ struct alx_priv *alx = netdev_priv(netdev);
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++ struct alx_hw *hw = &alx->hw;
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++
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++ if (wol->wolopts & ~(WAKE_MAGIC | WAKE_PHY))
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++ return -EOPNOTSUPP;
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++
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++ hw->sleep_ctrl = 0;
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++
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++ if (wol->wolopts & WAKE_MAGIC)
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++ hw->sleep_ctrl |= ALX_SLEEP_WOL_MAGIC;
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++ if (wol->wolopts & WAKE_PHY)
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++ hw->sleep_ctrl |= ALX_SLEEP_WOL_PHY;
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++
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++ device_set_wakeup_enable(&alx->hw.pdev->dev, hw->sleep_ctrl);
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++
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++ return 0;
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++}
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++
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+ const struct ethtool_ops alx_ethtool_ops = {
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+ .get_pauseparam = alx_get_pauseparam,
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+ .set_pauseparam = alx_set_pauseparam,
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+ .get_msglevel = alx_get_msglevel,
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+ .set_msglevel = alx_set_msglevel,
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++ .get_wol = alx_get_wol,
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++ .set_wol = alx_set_wol,
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+ .get_link = ethtool_op_get_link,
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+ .get_strings = alx_get_strings,
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+ .get_sset_count = alx_get_sset_count,
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+--- a/drivers/net/ethernet/atheros/alx/hw.c
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++++ b/drivers/net/ethernet/atheros/alx/hw.c
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+@@ -332,6 +332,16 @@ void alx_set_macaddr(struct alx_hw *hw, const u8 *addr)
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+ alx_write_mem32(hw, ALX_STAD1, val);
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+ }
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+
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++static void alx_enable_osc(struct alx_hw *hw)
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++{
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++ u32 val;
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++
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++ /* rising edge */
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++ val = alx_read_mem32(hw, ALX_MISC);
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++ alx_write_mem32(hw, ALX_MISC, val & ~ALX_MISC_INTNLOSC_OPEN);
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++ alx_write_mem32(hw, ALX_MISC, val | ALX_MISC_INTNLOSC_OPEN);
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++}
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++
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+ static void alx_reset_osc(struct alx_hw *hw, u8 rev)
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+ {
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+ u32 val, val2;
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+@@ -848,6 +858,66 @@ void alx_post_phy_link(struct alx_hw *hw)
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+ }
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+ }
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+
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++
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++/* NOTE:
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++ * 1. phy link must be established before calling this function
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++ * 2. wol option (pattern,magic,link,etc.) is configed before call it.
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++ */
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++int alx_pre_suspend(struct alx_hw *hw, int speed, u8 duplex)
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++{
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++ u32 master, mac, phy, val;
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++ int err = 0;
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++
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++ master = alx_read_mem32(hw, ALX_MASTER);
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++ master &= ~ALX_MASTER_PCLKSEL_SRDS;
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++ mac = hw->rx_ctrl;
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++ /* 10/100 half */
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++ ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED, ALX_MAC_CTRL_SPEED_10_100);
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++ mac &= ~(ALX_MAC_CTRL_FULLD | ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_TX_EN);
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++
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++ phy = alx_read_mem32(hw, ALX_PHY_CTRL);
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++ phy &= ~(ALX_PHY_CTRL_DSPRST_OUT | ALX_PHY_CTRL_CLS);
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++ phy |= ALX_PHY_CTRL_RST_ANALOG | ALX_PHY_CTRL_HIB_PULSE |
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++ ALX_PHY_CTRL_HIB_EN;
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++
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++ /* without any activity */
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++ if (!(hw->sleep_ctrl & ALX_SLEEP_ACTIVE)) {
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++ err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
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++ if (err)
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++ return err;
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++ phy |= ALX_PHY_CTRL_IDDQ | ALX_PHY_CTRL_POWER_DOWN;
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++ } else {
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++ if (hw->sleep_ctrl & (ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_CIFS))
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++ mac |= ALX_MAC_CTRL_RX_EN | ALX_MAC_CTRL_BRD_EN;
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++ if (hw->sleep_ctrl & ALX_SLEEP_CIFS)
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++ mac |= ALX_MAC_CTRL_TX_EN;
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++ if (duplex == DUPLEX_FULL)
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++ mac |= ALX_MAC_CTRL_FULLD;
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++ if (speed == SPEED_1000)
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++ ALX_SET_FIELD(mac, ALX_MAC_CTRL_SPEED,
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++ ALX_MAC_CTRL_SPEED_1000);
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++ phy |= ALX_PHY_CTRL_DSPRST_OUT;
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++ err = alx_write_phy_ext(hw, ALX_MIIEXT_ANEG,
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++ ALX_MIIEXT_S3DIG10,
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++ ALX_MIIEXT_S3DIG10_SL);
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++ if (err)
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++ return err;
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++ }
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++
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++ alx_enable_osc(hw);
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++ hw->rx_ctrl = mac;
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++ alx_write_mem32(hw, ALX_MASTER, master);
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++ alx_write_mem32(hw, ALX_MAC_CTRL, mac);
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++ alx_write_mem32(hw, ALX_PHY_CTRL, phy);
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++
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++ /* set val of PDLL D3PLLOFF */
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++ val = alx_read_mem32(hw, ALX_PDLL_TRNS1);
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++ val |= ALX_PDLL_TRNS1_D3PLLOFF_EN;
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++ alx_write_mem32(hw, ALX_PDLL_TRNS1, val);
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++
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++ return 0;
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++}
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++
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+ bool alx_phy_configured(struct alx_hw *hw)
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+ {
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+ u32 cfg, hw_cfg;
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+@@ -920,6 +990,26 @@ int alx_clear_phy_intr(struct alx_hw *hw)
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+ return alx_read_phy_reg(hw, ALX_MII_ISR, &isr);
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+ }
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+
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++int alx_config_wol(struct alx_hw *hw)
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++{
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++ u32 wol = 0;
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++ int err = 0;
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++
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++ /* turn on magic packet event */
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++ if (hw->sleep_ctrl & ALX_SLEEP_WOL_MAGIC)
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++ wol |= ALX_WOL0_MAGIC_EN | ALX_WOL0_PME_MAGIC_EN;
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++
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++ /* turn on link up event */
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++ if (hw->sleep_ctrl & ALX_SLEEP_WOL_PHY) {
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++ wol |= ALX_WOL0_LINK_EN | ALX_WOL0_PME_LINK;
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++ /* only link up can wake up */
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++ err = alx_write_phy_reg(hw, ALX_MII_IER, ALX_IER_LINK_UP);
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++ }
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++ alx_write_mem32(hw, ALX_WOL0, wol);
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++
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++ return err;
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++}
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++
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+ void alx_disable_rss(struct alx_hw *hw)
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+ {
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+ u32 ctrl = alx_read_mem32(hw, ALX_RXQ0);
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+@@ -1045,6 +1135,71 @@ void alx_mask_msix(struct alx_hw *hw, int index, bool mask)
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+ }
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+
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+
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++int alx_select_powersaving_speed(struct alx_hw *hw, int *speed, u8 *duplex)
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++{
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++ int i, err;
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++ u16 lpa;
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++
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++ err = alx_read_phy_link(hw);
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++ if (err)
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++ return err;
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++
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++ if (hw->link_speed == SPEED_UNKNOWN) {
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++ *speed = SPEED_UNKNOWN;
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++ *duplex = DUPLEX_UNKNOWN;
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++ return 0;
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++ }
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++
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++ err = alx_read_phy_reg(hw, MII_LPA, &lpa);
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++ if (err)
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++ return err;
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++
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++ if (!(lpa & LPA_LPACK)) {
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++ *speed = hw->link_speed;
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++ return 0;
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++ }
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++
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++ if (lpa & LPA_10FULL) {
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++ *speed = SPEED_10;
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++ *duplex = DUPLEX_FULL;
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++ } else if (lpa & LPA_10HALF) {
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++ *speed = SPEED_10;
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++ *duplex = DUPLEX_HALF;
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++ } else if (lpa & LPA_100FULL) {
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++ *speed = SPEED_100;
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++ *duplex = DUPLEX_FULL;
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++ } else {
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++ *speed = SPEED_100;
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++ *duplex = DUPLEX_HALF;
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++ }
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++
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++ if (*speed == hw->link_speed && *duplex == hw->duplex)
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++ return 0;
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++ err = alx_write_phy_reg(hw, ALX_MII_IER, 0);
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++ if (err)
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++ return err;
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++ err = alx_setup_speed_duplex(hw, alx_speed_to_ethadv(*speed, *duplex) |
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++ ADVERTISED_Autoneg, ALX_FC_ANEG |
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++ ALX_FC_RX | ALX_FC_TX);
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++ if (err)
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++ return err;
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++
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++ /* wait for linkup */
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++ for (i = 0; i < ALX_MAX_SETUP_LNK_CYCLE; i++) {
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++ msleep(100);
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++
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++ err = alx_read_phy_link(hw);
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++ if (err < 0)
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++ return err;
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++ if (hw->link_speed != SPEED_UNKNOWN)
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++ break;
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++ }
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++ if (i == ALX_MAX_SETUP_LNK_CYCLE)
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++ return -ETIMEDOUT;
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++
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++ return 0;
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++}
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++
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+ bool alx_get_phy_info(struct alx_hw *hw)
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+ {
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+ u16 devs1, devs2;
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+--- a/drivers/net/ethernet/atheros/alx/hw.h
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++++ b/drivers/net/ethernet/atheros/alx/hw.h
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+@@ -487,6 +487,8 @@ struct alx_hw {
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+ u8 flowctrl;
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+ u32 adv_cfg;
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+
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++ u32 sleep_ctrl;
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++
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+ spinlock_t mdio_lock;
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+ struct mdio_if_info mdio;
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+ u16 phy_id[2];
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+@@ -549,12 +551,14 @@ void alx_reset_pcie(struct alx_hw *hw);
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+ void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
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+ int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
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+ void alx_post_phy_link(struct alx_hw *hw);
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++int alx_pre_suspend(struct alx_hw *hw, int speed, u8 duplex);
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+ int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
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+ int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
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+ int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
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+ int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
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+ int alx_read_phy_link(struct alx_hw *hw);
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+ int alx_clear_phy_intr(struct alx_hw *hw);
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++int alx_config_wol(struct alx_hw *hw);
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+ void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
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+ void alx_start_mac(struct alx_hw *hw);
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+ int alx_reset_mac(struct alx_hw *hw);
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+@@ -563,6 +567,7 @@ bool alx_phy_configured(struct alx_hw *hw);
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+ void alx_configure_basic(struct alx_hw *hw);
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+ void alx_mask_msix(struct alx_hw *hw, int index, bool mask);
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+ void alx_disable_rss(struct alx_hw *hw);
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++int alx_select_powersaving_speed(struct alx_hw *hw, int *speed, u8 *duplex);
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+ bool alx_get_phy_info(struct alx_hw *hw);
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+ void alx_update_hw_stats(struct alx_hw *hw);
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+
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+--- a/drivers/net/ethernet/atheros/alx/main.c
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++++ b/drivers/net/ethernet/atheros/alx/main.c
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+@@ -1069,6 +1069,7 @@ static int alx_init_sw(struct alx_priv *alx)
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+ alx->dev->max_mtu = ALX_MAX_FRAME_LEN(ALX_MAX_FRAME_SIZE);
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+ alx->tx_ringsz = 256;
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+ alx->rx_ringsz = 512;
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++ hw->sleep_ctrl = ALX_SLEEP_WOL_MAGIC | ALX_SLEEP_WOL_PHY;
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+ hw->imt = 200;
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+ alx->int_mask = ALX_ISR_MISC;
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+ hw->dma_chnl = hw->max_dma_chnl;
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+@@ -1181,11 +1182,8 @@ static int alx_change_mtu(struct net_device *netdev, int mtu)
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+ alx->hw.mtu = mtu;
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+ alx->rxbuf_size = max(max_frame, ALX_DEF_RXBUF_SIZE);
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+ netdev_update_features(netdev);
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+- if (netif_running(netdev)) {
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+- mutex_lock(&alx->mtx);
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++ if (netif_running(netdev))
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+ alx_reinit(alx);
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+- mutex_unlock(&alx->mtx);
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+- }
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+ return 0;
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+ }
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+
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+@@ -1371,6 +1369,66 @@ static int alx_stop(struct net_device *netdev)
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+ return 0;
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+ }
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+
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++static int __alx_shutdown(struct pci_dev *pdev, bool *wol_en)
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++{
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++ struct alx_priv *alx = pci_get_drvdata(pdev);
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++ struct net_device *netdev = alx->dev;
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++ struct alx_hw *hw = &alx->hw;
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++ int err, speed;
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++ u8 duplex;
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++
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++ netif_device_detach(netdev);
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++
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++ if (netif_running(netdev))
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++ __alx_stop(alx);
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++
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++#ifdef CONFIG_PM_SLEEP
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++ err = pci_save_state(pdev);
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++ if (err)
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++ return err;
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++#endif
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++
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++ err = alx_select_powersaving_speed(hw, &speed, &duplex);
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++ if (err)
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++ return err;
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++ err = alx_clear_phy_intr(hw);
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++ if (err)
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++ return err;
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++ err = alx_pre_suspend(hw, speed, duplex);
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++ if (err)
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++ return err;
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++ err = alx_config_wol(hw);
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++ if (err)
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++ return err;
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++
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++ *wol_en = false;
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++ if (hw->sleep_ctrl & ALX_SLEEP_ACTIVE) {
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++ netif_info(alx, wol, netdev,
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++ "wol: ctrl=%X, speed=%X\n",
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++ hw->sleep_ctrl, speed);
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++ device_set_wakeup_enable(&pdev->dev, true);
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++ *wol_en = true;
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++ }
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++
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++ pci_disable_device(pdev);
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++
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++ return 0;
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++}
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++
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++static void alx_shutdown(struct pci_dev *pdev)
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++{
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++ int err;
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++ bool wol_en;
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++
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++ err = __alx_shutdown(pdev, &wol_en);
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++ if (!err) {
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++ pci_wake_from_d3(pdev, wol_en);
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++ pci_set_power_state(pdev, PCI_D3hot);
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++ } else {
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++ dev_err(&pdev->dev, "shutdown fail %d\n", err);
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++ }
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++}
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++
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+ static void alx_link_check(struct work_struct *work)
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+ {
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|
|
+ struct alx_priv *alx;
|
|
|
+@@ -1865,6 +1923,7 @@ static int alx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
+ goto out_unmap;
|
|
|
+ }
|
|
|
+
|
|
|
++ device_set_wakeup_enable(&pdev->dev, hw->sleep_ctrl);
|
|
|
+ netdev_info(netdev,
|
|
|
+ "Qualcomm Atheros AR816x/AR817x Ethernet [%pM]\n",
|
|
|
+ netdev->dev_addr);
|
|
|
+@@ -1910,16 +1969,26 @@ static int alx_suspend(struct device *dev)
|
|
|
+ {
|
|
|
+ struct alx_priv *alx = dev_get_drvdata(dev);
|
|
|
+
|
|
|
+- if (!netif_running(alx->dev))
|
|
|
+- return 0;
|
|
|
++ struct pci_dev *pdev = alx->hw.pdev;
|
|
|
++ int err;
|
|
|
++ bool wol_en;
|
|
|
+
|
|
|
+- rtnl_lock();
|
|
|
+- netif_device_detach(alx->dev);
|
|
|
++ //if (!netif_running(alx->dev))
|
|
|
++ // return 0;
|
|
|
++ //netif_device_detach(alx->dev);
|
|
|
++ //__alx_stop(alx);
|
|
|
++ err = __alx_shutdown(pdev, &wol_en);
|
|
|
++ if (err) {
|
|
|
++ dev_err(&pdev->dev, "shutdown fail in suspend %d\n", err);
|
|
|
++ return err;
|
|
|
++ }
|
|
|
+
|
|
|
+- mutex_lock(&alx->mtx);
|
|
|
+- __alx_stop(alx);
|
|
|
+- mutex_unlock(&alx->mtx);
|
|
|
+- rtnl_unlock();
|
|
|
++ if (wol_en) {
|
|
|
++ pci_prepare_to_sleep(pdev);
|
|
|
++ } else {
|
|
|
++ pci_wake_from_d3(pdev, false);
|
|
|
++ pci_set_power_state(pdev, PCI_D3hot);
|
|
|
++ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+@@ -1927,34 +1996,53 @@ static int alx_suspend(struct device *dev)
|
|
|
+ static int alx_resume(struct device *dev)
|
|
|
+ {
|
|
|
+ struct alx_priv *alx = dev_get_drvdata(dev);
|
|
|
++ struct net_device *netdev = alx->dev;
|
|
|
+ struct alx_hw *hw = &alx->hw;
|
|
|
++ struct pci_dev *pdev = hw->pdev;
|
|
|
+ int err;
|
|
|
+
|
|
|
+- rtnl_lock();
|
|
|
+ mutex_lock(&alx->mtx);
|
|
|
++
|
|
|
++ pci_set_power_state(pdev, PCI_D0);
|
|
|
++ pci_restore_state(pdev);
|
|
|
++ pci_save_state(pdev);
|
|
|
++
|
|
|
++ pci_enable_wake(pdev, PCI_D3hot, 0);
|
|
|
++ pci_enable_wake(pdev, PCI_D3cold, 0);
|
|
|
++
|
|
|
++ hw->link_speed = SPEED_UNKNOWN;
|
|
|
++ alx->int_mask = ALX_ISR_MISC;
|
|
|
++
|
|
|
++ alx_reset_pcie(hw);
|
|
|
+ alx_reset_phy(hw);
|
|
|
+
|
|
|
+- if (!netif_running(alx->dev)) {
|
|
|
+- err = 0;
|
|
|
+- goto unlock;
|
|
|
++ //if (!netif_running(alx->dev)) {
|
|
|
++ // err = 0;
|
|
|
++ // goto unlock;
|
|
|
++ //}
|
|
|
++ err = alx_reset_mac(hw);
|
|
|
++ if (err) {
|
|
|
++ netif_err(alx, hw, alx->dev, "resume:reset_mac fail %d\n", err);
|
|
|
++ err = -EIO;
|
|
|
++ goto unlock;
|
|
|
+ }
|
|
|
+
|
|
|
+- err = __alx_open(alx, true);
|
|
|
+- if (err)
|
|
|
+- goto unlock;
|
|
|
++ //err = __alx_open(alx, true);
|
|
|
++ //if (err)
|
|
|
++ // goto unlock;
|
|
|
++ if (netif_running(netdev)) {
|
|
|
++ err = __alx_open(alx, true);
|
|
|
++ if (err)
|
|
|
++ goto unlock;
|
|
|
++ }
|
|
|
+
|
|
|
+ netif_device_attach(alx->dev);
|
|
|
+
|
|
|
+ unlock:
|
|
|
+ mutex_unlock(&alx->mtx);
|
|
|
+- rtnl_unlock();
|
|
|
+ return err;
|
|
|
+ }
|
|
|
+
|
|
|
+-static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
|
|
|
+-#define ALX_PM_OPS (&alx_pm_ops)
|
|
|
+-#else
|
|
|
+-#define ALX_PM_OPS NULL
|
|
|
+ #endif
|
|
|
+
|
|
|
+
|
|
|
+@@ -2000,6 +2088,8 @@ static pci_ers_result_t alx_pci_error_slot_reset(struct pci_dev *pdev)
|
|
|
+ }
|
|
|
+
|
|
|
+ pci_set_master(pdev);
|
|
|
++ pci_enable_wake(pdev, PCI_D3hot, 0);
|
|
|
++ pci_enable_wake(pdev, PCI_D3cold, 0);
|
|
|
+
|
|
|
+ alx_reset_pcie(hw);
|
|
|
+ if (!alx_reset_mac(hw))
|
|
|
+@@ -2049,11 +2139,20 @@ static const struct pci_device_id alx_pci_tbl[] = {
|
|
|
+ {}
|
|
|
+ };
|
|
|
+
|
|
|
++#ifdef CONFIG_PM_SLEEP
|
|
|
++static SIMPLE_DEV_PM_OPS(alx_pm_ops, alx_suspend, alx_resume);
|
|
|
++#define ALX_PM_OPS (&alx_pm_ops)
|
|
|
++#else
|
|
|
++#define ALX_PM_OPS NULL
|
|
|
++#endif
|
|
|
++
|
|
|
++
|
|
|
+ static struct pci_driver alx_driver = {
|
|
|
+ .name = alx_drv_name,
|
|
|
+ .id_table = alx_pci_tbl,
|
|
|
+ .probe = alx_probe,
|
|
|
+ .remove = alx_remove,
|
|
|
++ .shutdown = alx_shutdown,
|
|
|
+ .err_handler = &alx_err_handlers,
|
|
|
+ .driver.pm = ALX_PM_OPS,
|
|
|
+ };
|