0002-add-xc6slx16-ucf-and-a-Makefile-for-xilinx-tools.patch 2.1 KB

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  1. From 1bdad90649f380ba652b6ff522646345c0b575c6 Mon Sep 17 00:00:00 2001
  2. From: Xiangfu <xiangfu@openmobilefree.net>
  3. Date: Mon, 1 Jul 2013 20:19:29 +0800
  4. Subject: [PATCH 2/2] add xc6slx16 ucf and a Makefile for xilinx tools
  5. ---
  6. bscan_spi/Makefile | 56 ++++++++++++++++++++++++++++++++++++++
  7. bscan_spi/bscan_s6_spi_isf_ext.ucf | 4 +++
  8. 2 files changed, 60 insertions(+)
  9. create mode 100644 bscan_spi/Makefile
  10. create mode 100644 bscan_spi/bscan_s6_spi_isf_ext.ucf
  11. diff --git a/bscan_spi/Makefile b/bscan_spi/Makefile
  12. new file mode 100644
  13. index 0000000..59dad6b
  14. --- /dev/null
  15. +++ b/bscan_spi/Makefile
  16. @@ -0,0 +1,56 @@
  17. +#
  18. +# Author: Xiangfu Liu
  19. +#
  20. +# This is free and unencumbered software released into the public domain.
  21. +# For details see the UNLICENSE file at the root of the source tree.
  22. +#
  23. +
  24. +all: bscan_s6_spi_isf_ext.bit
  25. +
  26. +# Build for m1
  27. +#FPGA_TARGET ?= xc6slx45-fgg484-2
  28. +
  29. +# Build for mini-slx9 board tqg144/ftg256/csg324
  30. +#FPGA_TARGET ?= xc6slx9-2-csg324
  31. +#FPGA_TARGET ?= xc6slx9-2-ftg256
  32. +FPGA_TARGET ?= xc6slx16-2-ftg256
  33. +
  34. +%.bit: %-routed.ncd
  35. +# -d disables DRC
  36. +# -b creates rawbits file .rbt
  37. +# -l creates logic allocation file .ll
  38. +# -w overwrite existing output file
  39. +# "-g compress" enables compression
  40. + if test -f $<; then bitgen -b -l -w $< $@; fi
  41. + mkdir -p bits
  42. + cp $@ bits/$(FPGA_TARGET).$@
  43. +
  44. +%.ncd: %.xdl
  45. + -xdl -xdl2ncd $<
  46. +
  47. +%-routed.ncd: %.ncd
  48. + par -w $< $@
  49. +
  50. +%.ncd: %.ngd
  51. + map -w $<
  52. +
  53. +%.ngd: %.ucf %.ngc
  54. + ngdbuild -uc $< $(@:.ngd=.ngc)
  55. +
  56. +%.ngc: %.xst
  57. + xst -ifn $<
  58. +
  59. +%.xst: %.prj
  60. + echo run > $@
  61. + echo -ifn $< >> $@
  62. + echo -top top >> $@
  63. + echo -ifmt MIXED >> $@
  64. + echo -opt_mode SPEED >> $@
  65. + echo -opt_level 1 >> $@
  66. + echo -ofn $(<:.prj=.ngc) >> $@
  67. + echo -p $(FPGA_TARGET) >> $@
  68. +
  69. +%.prj: %.v
  70. + for i in `echo $^`; do \
  71. + echo "verilog $(basename $<) $$i" >> $@; \
  72. + done
  73. diff --git a/bscan_spi/bscan_s6_spi_isf_ext.ucf b/bscan_spi/bscan_s6_spi_isf_ext.ucf
  74. new file mode 100644
  75. index 0000000..48098cd
  76. --- /dev/null
  77. +++ b/bscan_spi/bscan_s6_spi_isf_ext.ucf
  78. @@ -0,0 +1,4 @@
  79. +net "MISO" LOC = "P10";
  80. +net "MOSI" LOC = "T10";
  81. +net "DRCK1" LOC= "R11";
  82. +net "CSB" LOC = "T3";
  83. --
  84. 1.8.1.2